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drm/i915/dp: read Aux RD interval just before setting the FFE preset

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Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of
DP2.1a spec.
After reading LANEx_CHANNEL_EQ_DONE, read the FFE presets.
AUX_RD_INTERVAL and then write the new FFE presets.

v4: Read AUX_RD_INTERVAL before get/set TX FFE preset (Jani)

Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241011045825.2629469-1-arun.r.murthy@intel.com
This commit is contained in:
Arun R Murthy
2024-10-11 10:28:25 +05:30
committed by Suraj Kandpal
parent af02ee4fb6
commit eb0c1757a3
1 changed files with 8 additions and 7 deletions
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15
drivers/gpu/drm/i915/display/intel_dp_link_training.c
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@@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
for (try = 0; try < max_tries; try++) {
fsleep(delay_us);
/*
* The delay may get updated. The transmitter shall read the
* delay before link status during link training.
*/
delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
return false;
@@ -1451,8 +1445,15 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
if (time_after(jiffies, deadline))
timeout = true; /* try one last time after deadline */
/* Update signal levels and training set as requested. */
/*
* During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE
* presets.
*/
delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
/* Update signal levels and training set as requested. */
if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
return false;