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drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms

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Like most other plane control register bits, the pipe gamma
enable bit is also blocked by CxSR. So make sure we kick the
machine out of CxSR before trying to change that bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622155452.32587-8-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
This commit is contained in:
Ville Syrjälä
2022-06-22 18:54:50 +03:00
parent 8c45f31c32
commit eadbd86717
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/i915/display/intel_color.c
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@@ -1287,6 +1287,10 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
return PTR_ERR(plane_state);
new_crtc_state->update_planes |= BIT(plane->id);
/* plane control register changes blocked by CxSR */
if (HAS_GMCH(dev_priv))
new_crtc_state->disable_cxsr = true;
}
return 0;