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drm/amd/display: Update idle hardmins if uclk or fclk requirement changed

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[WHY&HOW]
Update the idle hardmin with SMU if either clock changed.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone
2024-05-31 18:09:48 -04:00
committed by Alex Deucher
parent d6b54900c5
commit ea9b3dbc71
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
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@@ -940,7 +940,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
}
/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
if (update_idle_uclk && is_idle_dpm_enabled) {
if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;