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drm/amd/ras: Add thread to handle ras events
Add thread to handle ras events. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
YiPeng Chai
committed by
Alex Deucher
Alex Deucher
parent
19030244e1
commit
ea61341b90
315
drivers/gpu/drm/amd/ras/rascore/ras_process.c
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315
drivers/gpu/drm/amd/ras/rascore/ras_process.c
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@@ -0,0 +1,315 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "ras.h"
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#include "ras_process.h"
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#define RAS_EVENT_FIFO_SIZE (128 * sizeof(struct ras_event_req))
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#define RAS_POLLING_ECC_TIMEOUT 300
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static int ras_process_put_event(struct ras_core_context *ras_core,
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struct ras_event_req *req)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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int ret;
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ret = kfifo_in_spinlocked(&ras_proc->event_fifo,
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req, sizeof(*req), &ras_proc->fifo_spinlock);
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if (!ret) {
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RAS_DEV_ERR(ras_core->dev, "Poison message fifo is full!\n");
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return -ENOSPC;
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}
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return 0;
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}
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static int ras_process_add_reset_gpu_event(struct ras_core_context *ras_core,
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uint32_t reset_cause)
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{
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struct ras_event_req req = {0};
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req.reset = reset_cause;
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return ras_process_put_event(ras_core, &req);
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}
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static int ras_process_get_event(struct ras_core_context *ras_core,
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struct ras_event_req *req)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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return kfifo_out_spinlocked(&ras_proc->event_fifo,
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req, sizeof(*req), &ras_proc->fifo_spinlock);
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}
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static void ras_process_clear_event_fifo(struct ras_core_context *ras_core)
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{
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struct ras_event_req req;
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int ret;
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do {
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ret = ras_process_get_event(ras_core, &req);
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} while (ret);
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}
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#define AMDGPU_RAS_WAITING_DATA_READY 200
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static int ras_process_umc_event(struct ras_core_context *ras_core,
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uint32_t event_count)
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{
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struct ras_ecc_count ecc_data;
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int ret = 0;
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uint32_t timeout = 0;
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uint32_t detected_de_count = 0;
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do {
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memset(&ecc_data, 0, sizeof(ecc_data));
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ret = ras_core_update_ecc_info(ras_core);
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if (ret)
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return ret;
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ret = ras_core_query_block_ecc_data(ras_core, RAS_BLOCK_ID__UMC, &ecc_data);
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if (ret)
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return ret;
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if (ecc_data.new_de_count) {
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detected_de_count += ecc_data.new_de_count;
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timeout = 0;
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} else {
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if (!timeout && event_count)
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timeout = AMDGPU_RAS_WAITING_DATA_READY;
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if (timeout) {
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if (!--timeout)
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break;
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msleep(1);
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}
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}
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} while (detected_de_count < event_count);
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if (detected_de_count && ras_core_gpu_is_rma(ras_core))
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ras_process_add_reset_gpu_event(ras_core, GPU_RESET_CAUSE_RMA);
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return 0;
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}
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static int ras_process_non_umc_event(struct ras_core_context *ras_core)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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struct ras_event_req req;
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uint32_t event_count = kfifo_len(&ras_proc->event_fifo);
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uint32_t reset_flags = 0;
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int ret = 0, i;
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for (i = 0; i < event_count; i++) {
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memset(&req, 0, sizeof(req));
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ret = ras_process_get_event(ras_core, &req);
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if (!ret)
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continue;
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ras_core_event_notify(ras_core,
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RAS_EVENT_ID__POISON_CONSUMPTION, &req);
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reset_flags |= req.reset;
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if (req.reset == GPU_RESET_CAUSE_RMA)
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continue;
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if (req.reset)
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} GPU reset for %s RAS poison consumption is issued!\n",
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req.seqno, ras_core_get_ras_block_name(req.block));
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else
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} %s RAS poison consumption is issued!\n",
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req.seqno, ras_core_get_ras_block_name(req.block));
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}
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if (reset_flags) {
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ret = ras_core_event_notify(ras_core,
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RAS_EVENT_ID__RESET_GPU, &reset_flags);
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if (!ret && (reset_flags & GPU_RESET_CAUSE_RMA))
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return -RAS_CORE_GPU_IN_MODE1_RESET;
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}
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return ret;
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}
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int ras_process_handle_ras_event(struct ras_core_context *ras_core)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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uint32_t umc_event_count;
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int ret;
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ras_aca_clear_fatal_flag(ras_core);
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ras_umc_log_pending_bad_bank(ras_core);
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do {
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umc_event_count = atomic_read(&ras_proc->umc_interrupt_count);
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ret = ras_process_umc_event(ras_core, umc_event_count);
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if (ret == -RAS_CORE_GPU_IN_MODE1_RESET)
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break;
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if (umc_event_count)
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atomic_sub(umc_event_count, &ras_proc->umc_interrupt_count);
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} while (atomic_read(&ras_proc->umc_interrupt_count));
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if ((ret != -RAS_CORE_GPU_IN_MODE1_RESET) &&
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(kfifo_len(&ras_proc->event_fifo)))
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ret = ras_process_non_umc_event(ras_core);
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if (ret == -RAS_CORE_GPU_IN_MODE1_RESET) {
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/* Clear poison fifo */
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ras_process_clear_event_fifo(ras_core);
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atomic_set(&ras_proc->umc_interrupt_count, 0);
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}
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return ret;
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}
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static int thread_wait_condition(void *param)
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{
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struct ras_process *ras_proc = (struct ras_process *)param;
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return (kthread_should_stop() ||
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atomic_read(&ras_proc->ras_interrupt_req));
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}
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static int ras_process_thread(void *context)
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{
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struct ras_core_context *ras_core = (struct ras_core_context *)context;
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struct ras_process *ras_proc = &ras_core->ras_proc;
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while (!kthread_should_stop()) {
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ras_wait_event_interruptible_timeout(&ras_proc->ras_process_wq,
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thread_wait_condition, ras_proc,
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msecs_to_jiffies(RAS_POLLING_ECC_TIMEOUT));
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if (kthread_should_stop())
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break;
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if (!ras_core->is_initialized)
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continue;
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atomic_set(&ras_proc->ras_interrupt_req, 0);
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if (ras_core_gpu_in_reset(ras_core))
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continue;
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if (ras_core->sys_fn && ras_core->sys_fn->async_handle_ras_event)
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ras_core->sys_fn->async_handle_ras_event(ras_core, NULL);
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else
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ras_process_handle_ras_event(ras_core);
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}
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return 0;
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}
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int ras_process_init(struct ras_core_context *ras_core)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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int ret;
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ret = kfifo_alloc(&ras_proc->event_fifo, RAS_EVENT_FIFO_SIZE, GFP_KERNEL);
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if (ret)
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return ret;
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spin_lock_init(&ras_proc->fifo_spinlock);
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init_waitqueue_head(&ras_proc->ras_process_wq);
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ras_proc->ras_process_thread = kthread_run(ras_process_thread,
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(void *)ras_core, "ras_process_thread");
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if (!ras_proc->ras_process_thread) {
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RAS_DEV_ERR(ras_core->dev, "Failed to create ras_process_thread.\n");
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ret = -ENOMEM;
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goto err;
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}
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return 0;
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err:
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ras_process_fini(ras_core);
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return ret;
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}
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int ras_process_fini(struct ras_core_context *ras_core)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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if (ras_proc->ras_process_thread) {
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kthread_stop(ras_proc->ras_process_thread);
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ras_proc->ras_process_thread = NULL;
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}
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kfifo_free(&ras_proc->event_fifo);
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return 0;
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}
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static int ras_process_add_umc_interrupt_req(struct ras_core_context *ras_core,
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struct ras_event_req *req)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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atomic_inc(&ras_proc->umc_interrupt_count);
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atomic_inc(&ras_proc->ras_interrupt_req);
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wake_up(&ras_proc->ras_process_wq);
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return 0;
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}
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static int ras_process_add_non_umc_interrupt_req(struct ras_core_context *ras_core,
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struct ras_event_req *req)
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{
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struct ras_process *ras_proc = &ras_core->ras_proc;
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int ret;
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ret = ras_process_put_event(ras_core, req);
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if (!ret) {
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atomic_inc(&ras_proc->ras_interrupt_req);
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wake_up(&ras_proc->ras_process_wq);
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}
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return ret;
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}
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int ras_process_add_interrupt_req(struct ras_core_context *ras_core,
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struct ras_event_req *req, bool is_umc)
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{
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int ret;
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if (!ras_core)
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return -EINVAL;
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if (!ras_core->is_initialized)
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return -EPERM;
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if (is_umc)
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ret = ras_process_add_umc_interrupt_req(ras_core, req);
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else
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ret = ras_process_add_non_umc_interrupt_req(ras_core, req);
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return ret;
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}
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53
drivers/gpu/drm/amd/ras/rascore/ras_process.h
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53
drivers/gpu/drm/amd/ras/rascore/ras_process.h
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@@ -0,0 +1,53 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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||||
*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RAS_PROCESS_H__
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#define __RAS_PROCESS_H__
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struct ras_event_req {
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uint64_t seqno;
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uint32_t idx_vf;
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uint32_t block;
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uint16_t pasid;
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uint32_t reset;
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void *pasid_fn;
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void *data;
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};
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struct ras_process {
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void *dev;
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void *ras_process_thread;
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wait_queue_head_t ras_process_wq;
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atomic_t ras_interrupt_req;
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atomic_t umc_interrupt_count;
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struct kfifo event_fifo;
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spinlock_t fifo_spinlock;
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};
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struct ras_core_context;
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int ras_process_init(struct ras_core_context *ras_core);
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int ras_process_fini(struct ras_core_context *ras_core);
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int ras_process_handle_ras_event(struct ras_core_context *ras_core);
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int ras_process_add_interrupt_req(struct ras_core_context *ras_core,
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struct ras_event_req *req, bool is_umc);
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#endif
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