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arm64: zynqmp: Disable Tri-state for MIO38 Pin
gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-state is enabled for MIO38, causing inappropriate PHY register reads. Disabled Tri-state for MIO38 to make HW reset work. Tri-state disable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7a3 00000540 Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 00000540 Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Link: https://lore.kernel.org/r/9f8a0687be407a8ffad610087074e94ebc4f5982.1704728353.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
committed by
Michal Simek
parent
24e85ff034
commit
ea470fe330
@@ -169,6 +169,25 @@ phy0: ethernet-phy@1 {
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&pinctrl0 {
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status = "okay";
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pinctrl_gpio0_default: gpio0-default {
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conf {
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groups = "gpio0_38_grp";
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bias-pull-up;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_38_grp";
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function = "gpio0";
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};
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conf-tx {
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pins = "MIO38";
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bias-disable;
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output-enable;
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};
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};
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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@@ -324,6 +343,12 @@ mux {
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};
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};
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&gpio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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@@ -152,6 +152,25 @@ phy0: ethernet-phy@1 {
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&pinctrl0 {
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status = "okay";
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pinctrl_gpio0_default: gpio0-default {
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conf {
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groups = "gpio0_38_grp";
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bias-pull-up;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_38_grp";
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function = "gpio0";
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};
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conf-tx {
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pins = "MIO38";
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bias-disable;
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output-enable;
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};
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};
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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@@ -307,6 +326,12 @@ mux {
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};
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};
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&gpio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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