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drm/amdgpu/gfx6: drop all BUG()s
There's no need to crash the kernel for these cases. Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -347,7 +347,8 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
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case CHIP_HAINAN:
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chip_name = "hainan";
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break;
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default: BUG();
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default:
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return -EINVAL;
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}
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err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
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@@ -1736,8 +1737,8 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
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gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
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break;
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default:
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BUG();
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break;
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dev_warn(adev->dev, "Unsupported asic_type 0x%08x\n", adev->asic_type);
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return;
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}
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WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
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@@ -2202,7 +2203,7 @@ static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
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else if (ring == &adev->gfx.compute_ring[1])
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return RREG32(mmCP_RB2_WPTR);
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else
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BUG();
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return 0;
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}
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static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
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@@ -2223,8 +2224,6 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
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} else if (ring == &adev->gfx.compute_ring[1]) {
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WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
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(void)RREG32(mmCP_RB2_WPTR);
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} else {
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BUG();
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}
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}
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@@ -3310,7 +3309,6 @@ static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
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}
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default:
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BUG();
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break;
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}
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