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iommu/arm-smmu-v3: Add a type for the CD entry
Instead of passing a naked __le16 * around to represent a CD table entry wrap it in a "struct arm_smmu_cd" with an array of the correct size. This makes it much clearer which functions will comprise the "CD API". Tested-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Michael Shavit <mshavit@google.com> Reviewed-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Mostafa Saleh <smostafa@google.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/5-v6-228e7adf25eb+4155-smmuv3_newapi_p2_jgg@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
committed by
Will Deacon
parent
86e5ca098d
commit
e8e4398d53
@@ -1209,7 +1209,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst,
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WRITE_ONCE(*dst, cpu_to_le64(val));
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}
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static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid)
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static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master,
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u32 ssid)
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{
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__le64 *l1ptr;
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unsigned int idx;
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@@ -1218,7 +1219,8 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid)
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struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table;
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if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR)
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return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS;
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return (struct arm_smmu_cd *)(cd_table->cdtab +
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ssid * CTXDESC_CD_DWORDS);
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idx = ssid >> CTXDESC_SPLIT;
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l1_desc = &cd_table->l1_desc[idx];
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@@ -1232,7 +1234,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid)
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arm_smmu_sync_cd(master, ssid, false);
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}
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idx = ssid & (CTXDESC_L2_ENTRIES - 1);
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return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS;
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return &l1_desc->l2ptr[idx];
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}
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int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,
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@@ -1251,7 +1253,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,
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*/
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u64 val;
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bool cd_live;
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__le64 *cdptr;
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struct arm_smmu_cd *cdptr;
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struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table;
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struct arm_smmu_device *smmu = master->smmu;
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@@ -1262,7 +1264,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,
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if (!cdptr)
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return -ENOMEM;
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val = le64_to_cpu(cdptr[0]);
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val = le64_to_cpu(cdptr->data[0]);
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cd_live = !!(val & CTXDESC_CD_0_V);
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if (!cd) { /* (5) */
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@@ -1279,9 +1281,9 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,
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* this substream's traffic
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*/
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} else { /* (1) and (2) */
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cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK);
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cdptr[2] = 0;
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cdptr[3] = cpu_to_le64(cd->mair);
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cdptr->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK);
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cdptr->data[2] = 0;
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cdptr->data[3] = cpu_to_le64(cd->mair);
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/*
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* STE may be live, and the SMMU might read dwords of this CD in any
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@@ -1313,7 +1315,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,
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* field within an aligned 64-bit span of a structure can be altered
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* without first making the structure invalid.
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*/
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WRITE_ONCE(cdptr[0], cpu_to_le64(val));
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WRITE_ONCE(cdptr->data[0], cpu_to_le64(val));
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arm_smmu_sync_cd(master, ssid, true);
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return 0;
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}
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@@ -283,6 +283,11 @@ struct arm_smmu_ste {
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#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
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#define CTXDESC_CD_DWORDS 8
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struct arm_smmu_cd {
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__le64 data[CTXDESC_CD_DWORDS];
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};
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#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
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#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
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#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
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@@ -592,7 +597,7 @@ struct arm_smmu_ctx_desc {
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};
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struct arm_smmu_l1_ctx_desc {
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__le64 *l2ptr;
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struct arm_smmu_cd *l2ptr;
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dma_addr_t l2ptr_dma;
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};
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