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drm/amd/display: enable dcn315/316 s0i2 support

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[why]
enable the support in driver, let the control by CMOS

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu
2022-02-25 20:50:14 -05:00
committed by Alex Deucher
parent 4185f99094
commit e7145aaedd
2 changed files with 2 additions and 3 deletions
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2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
View File

@@ -131,6 +131,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
union display_idle_optimization_u idle_info = { 0 };
idle_info.idle_info.df_request_disabled = 1;
idle_info.idle_info.phy_ref_clk_off = 1;
idle_info.idle_info.s0i2_rdy = 1;
dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
/* update power state */
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
@@ -526,7 +527,6 @@ void dcn315_clk_mgr_construct(
struct dccg *dccg)
{
struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
struct clk_mgr *clk_mgr_base = ctx->dc->clk_mgr;
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn315_funcs;

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
View File

@@ -172,8 +172,7 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
union display_idle_optimization_u idle_info = { 0 };
idle_info.idle_info.df_request_disabled = 1;
idle_info.idle_info.phy_ref_clk_off = 1;
// Todo DCN316 set this to 1 if any no issue
idle_info.idle_info.s0i2_rdy = 0;
idle_info.idle_info.s0i2_rdy = 1;
dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
/* update power state */
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;