drm/amd/display: Pass debug watermarks through to DCN35 DML2

[Why]
The DC debug options currently do not function for dynamically adjusting
our watermarks.

[How]
Hook them up before passing them to DML2.
Also make sure we're using dc->bb_overrides since dc->debug isn't
populated during dc_construct.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
2023-12-01 06:25:12 -07:00
committed by Alex Deucher
parent c59397eff9
commit e6ae4c47e8

View File

@@ -326,6 +326,25 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
dcn3_5_soc.dram_clock_change_latency_us =
dc->debug.dram_clock_change_latency_ns / 1000.0;
}
if (dc->bb_overrides.dram_clock_change_latency_ns > 0)
dcn3_5_soc.dram_clock_change_latency_us =
dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
if (dc->bb_overrides.sr_exit_time_ns > 0)
dcn3_5_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)
dcn3_5_soc.sr_enter_plus_exit_time_us =
dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
if (dc->bb_overrides.sr_exit_z8_time_ns > 0)
dcn3_5_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;
if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)
dcn3_5_soc.sr_enter_plus_exit_z8_time_us =
dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;
/*temp till dml2 fully work without dml1*/
dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,
DML_PROJECT_DCN31);