mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-03 22:57:21 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amdgpu: Add some XCC programming

Browse Source 
Add additional XCC programming sequences.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
2022-02-18 15:04:35 +05:30
committed by Alex Deucher
parent 15091a6f43
commit e6a02e2cc7
1 changed files with 26 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
View File

@@ -1150,6 +1150,29 @@ static void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
WREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG, data);
}
static void gfx_v9_4_3_program_xcc_id(struct amdgpu_device *adev, int xcc_id)
{
uint32_t tmp = 0;
switch (adev->gfx.num_xcd) {
/* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */
case 1:
WREG32_SOC15(GC, xcc_id, regCP_HYP_XCP_CTL, 0x8);
break;
case 2:
tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID);
tmp = tmp | (adev->gfx.num_xcd << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP));
WREG32_SOC15(GC, xcc_id, regCP_HYP_XCP_CTL, tmp);
tmp = xcc_id << REG_FIELD_SHIFT(CP_PSP_XCP_CTL, PHYSICAL_XCC_ID);
tmp = tmp | (xcc_id << REG_FIELD_SHIFT(CP_PSP_XCP_CTL, XCC_DIE_ID));
WREG32_SOC15(GC, xcc_id, regCP_PSP_XCP_CTL, tmp);
break;
default:
break;
}
}
static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
{
uint32_t rlc_setting;
@@ -1948,6 +1971,9 @@ static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
return r;
}
/* set the virtual and physical id based on partition_mode */
gfx_v9_4_3_program_xcc_id(adev, i);
r = gfx_v9_4_3_kiq_resume(adev, i);
if (r)
return r;