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ath11k: add data path support for QCN9074

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hal rx descriptor is different for QCN9074 target type. since
rx_msdu_end, rx_msdu_start, rx_mpdu_start elements are in
different placement/alignment. In order to have generic data path,
introduce platform specific hal rx descriptor access ops in
ath11k_hw_ops.

Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1

Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org>
Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1612946530-28504-9-git-send-email-akolli@codeaurora.org
This commit is contained in:
Karthikeyan Periyasamy
2021-02-16 09:16:23 +02:00
committed by Kalle Valo
parent 6fe6f68fef
commit e678fbd401
8 changed files with 912 additions and 236 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/wireless/ath/ath11k/core.c
View File

@@ -69,6 +69,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.idle_ps = false,
.cold_boot_calib = true,
.supports_suspend = false,
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
},
{
.hw_rev = ATH11K_HW_IPQ6018_HW10,
@@ -108,6 +109,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.idle_ps = false,
.cold_boot_calib = true,
.supports_suspend = false,
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
},
{
.name = "qca6390 hw2.0",
@@ -146,6 +148,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.idle_ps = true,
.cold_boot_calib = false,
.supports_suspend = true,
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
},
{
.name = "qcn9074 hw1.0",
@@ -175,6 +178,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.idle_ps = false,
.cold_boot_calib = false,
.supports_suspend = false,
.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
},
};

474
drivers/net/wireless/ath/ath11k/dp_rx.c
View File

File diff suppressed because it is too large Load Diff

2
drivers/net/wireless/ath/ath11k/hal.h
View File

@@ -316,8 +316,6 @@ struct ath11k_base;
#define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
#define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff
#define HAL_RX_DESC_SIZE (sizeof(struct hal_rx_desc))
/* Add any other errors here and return them in
* ath11k_hal_rx_desc_get_err().
*/

2
drivers/net/wireless/ath/ath11k/hal_tx.c
View File

@@ -76,7 +76,7 @@ void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd,
ti->bss_ast_hash);
tcl_cmd->info4 = 0;
if (ti->enable_mesh && ab->hw_params.hw_ops->tx_mesh_enable)
if (ti->enable_mesh)
ab->hw_params.hw_ops->tx_mesh_enable(ab, tcl_cmd);
}

424
drivers/net/wireless/ath/ath11k/hw.c
View File

@@ -169,12 +169,358 @@ static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
return mac_id;
}
static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
__le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
}
static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
__le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
__le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
}
static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
{
return desc->u.ipq8074.hdr_status;
}
static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
{
return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
}
static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
__le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
}
static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
__le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
}
static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
__le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
}
static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
__le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
}
static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info1));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_SGI,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
}
static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
{
return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data);
}
static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
__le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
}
static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO2_TID,
__le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
}
static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
{
return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id);
}
static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
struct hal_rx_desc *ldesc)
{
memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end,
sizeof(struct rx_msdu_end_ipq8074));
memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention,
sizeof(struct rx_attention));
memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end,
sizeof(struct rx_mpdu_end));
}
static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
{
return FIELD_GET(HAL_TLV_HDR_TAG,
__le32_to_cpu(desc->u.ipq8074.mpdu_start_tag));
}
static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
{
return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id);
}
static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
{
u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1);
info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info);
}
static
struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc)
{
return &desc->u.ipq8074.attention;
}
static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
{
return &desc->u.ipq8074.msdu_payload[0];
}
static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU,
__le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
}
static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU,
__le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING,
__le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
}
static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
{
return desc->u.qcn9074.hdr_status;
}
static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
{
return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID;
}
static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE,
__le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
}
static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID,
__le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
}
static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID,
__le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
}
static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM,
__le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
}
static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info1));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_SGI,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
}
static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
{
return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data);
}
static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
__le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
}
static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO9_TID,
__le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
}
static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
{
return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id);
}
static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
struct hal_rx_desc *ldesc)
{
memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end,
sizeof(struct rx_msdu_end_qcn9074));
memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention,
sizeof(struct rx_attention));
memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end,
sizeof(struct rx_mpdu_end));
}
static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
{
return FIELD_GET(HAL_TLV_HDR_TAG,
__le32_to_cpu(desc->u.qcn9074.mpdu_start_tag));
}
static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
{
return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id);
}
static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
{
u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1);
info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info);
}
static
struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc)
{
return &desc->u.qcn9074.attention;
}
static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
{
return &desc->u.qcn9074.msdu_payload[0];
}
const struct ath11k_hw_ops ipq8074_ops = {
.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
.wmi_init_config = ath11k_init_wmi_config_ipq8074,
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
};
const struct ath11k_hw_ops ipq6018_ops = {
@@ -183,6 +529,32 @@ const struct ath11k_hw_ops ipq6018_ops = {
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
};
const struct ath11k_hw_ops qca6390_ops = {
@@ -191,6 +563,32 @@ const struct ath11k_hw_ops qca6390_ops = {
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
};
const struct ath11k_hw_ops qcn9074_ops = {
@@ -199,6 +597,32 @@ const struct ath11k_hw_ops qcn9074_ops = {
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
.tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
.rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
.rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
.rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
.rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
.rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
.rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
.rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
.rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
.rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
.rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
.rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
.rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
.rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
.rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
.rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
.rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
.rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
.rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
.rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
.rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
};
#define ATH11K_TX_RING_MASK_0 0x1

29
drivers/net/wireless/ath/ath11k/hw.h
View File

@@ -105,6 +105,7 @@ enum ath11k_bus {
#define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
struct hal_rx_desc;
struct hal_tcl_data_cmd;
struct ath11k_hw_ring_mask {
@@ -160,6 +161,7 @@ struct ath11k_hw_params {
bool idle_ps;
bool cold_boot_calib;
bool supports_suspend;
u32 hal_desc_sz;
};
struct ath11k_hw_ops {
@@ -170,6 +172,33 @@ struct ath11k_hw_ops {
int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
void (*tx_mesh_enable)(struct ath11k_base *ab,
struct hal_tcl_data_cmd *tcl_cmd);
bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
struct hal_rx_desc *ldesc);
u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
};
extern const struct ath11k_hw_ops ipq8074_ops;

1
drivers/net/wireless/ath/ath11k/pci.c
View File

@@ -775,6 +775,7 @@ static int ath11k_pci_config_irq(struct ath11k_base *ab)
}
ab->irq_num[irq_idx] = irq;
ath11k_pci_ce_irq_disable(ab, i);
}

212
drivers/net/wireless/ath/ath11k/rx_desc.h
View File

@@ -414,7 +414,7 @@ struct rx_attention {
#define RX_MPDU_START_RAW_MPDU BIT(0)
struct rx_mpdu_start {
struct rx_mpdu_start_ipq8074 {
__le16 info0;
__le16 phy_ppdu_id;
__le16 ast_index;
@@ -440,6 +440,112 @@ struct rx_mpdu_start {
__le32 raw;
} __packed;
#define RX_MPDU_START_INFO7_REO_DEST_IND GENMASK(4, 0)
#define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB GENMASK(6, 5)
#define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ BIT(7)
#define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA BIT(8)
#define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA BIT(9)
#define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR BIT(10)
#define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL GENMASK(12, 11)
#define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL GENMASK(14, 13)
#define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI GENMASK(7, 0)
#define RX_MPDU_START_INFO8_RECV_QUEUE_NUM GENMASK(23, 8)
#define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN BIT(24)
#define RX_MPDU_START_INFO8_FIRST_DELIM_ERR BIT(25)
#define RX_MPDU_START_INFO9_EPD_EN BIT(0)
#define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD BIT(1)
#define RX_MPDU_START_INFO9_ENC_TYPE GENMASK(5, 2)
#define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
#define RX_MPDU_START_INFO9_MESH_STA GENMASK(9, 8)
#define RX_MPDU_START_INFO9_BSSID_HIT BIT(10)
#define RX_MPDU_START_INFO9_BSSID_NUM GENMASK(14, 11)
#define RX_MPDU_START_INFO9_TID GENMASK(18, 15)
#define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR GENMASK(1, 0)
#define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID GENMASK(8, 2)
#define RX_MPDU_START_INFO10_NDP_FRAME BIT(9)
#define RX_MPDU_START_INFO10_PHY_ERR BIT(10)
#define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR BIT(11)
#define RX_MPDU_START_INFO10_PROTO_VER_ERR BIT(12)
#define RX_MPDU_START_INFO10_AST_LOOKUP_VALID BIT(13)
#define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID BIT(0)
#define RX_MPDU_START_INFO11_MPDU_DUR_VALID BIT(1)
#define RX_MPDU_START_INFO11_MAC_ADDR1_VALID BIT(2)
#define RX_MPDU_START_INFO11_MAC_ADDR2_VALID BIT(3)
#define RX_MPDU_START_INFO11_MAC_ADDR3_VALID BIT(4)
#define RX_MPDU_START_INFO11_MAC_ADDR4_VALID BIT(5)
#define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID BIT(6)
#define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID BIT(7)
#define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID BIT(8)
#define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID BIT(9)
#define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER GENMASK(13, 10)
#define RX_MPDU_START_INFO11_MORE_FRAG_FLAG BIT(14)
#define RX_MPDU_START_INFO11_FROM_DS BIT(16)
#define RX_MPDU_START_INFO11_TO_DS BIT(17)
#define RX_MPDU_START_INFO11_ENCRYPTED BIT(18)
#define RX_MPDU_START_INFO11_MPDU_RETRY BIT(19)
#define RX_MPDU_START_INFO11_MPDU_SEQ_NUM GENMASK(31, 20)
#define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0)
#define RX_MPDU_START_INFO12_NEW_PEER_ENTRY BIT(8)
#define RX_MPDU_START_INFO12_DECRYPT_NEEDED BIT(9)
#define RX_MPDU_START_INFO12_DECAP_TYPE GENMASK(11, 10)
#define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING BIT(12)
#define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING BIT(13)
#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C BIT(14)
#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S BIT(15)
#define RX_MPDU_START_INFO12_PRE_DELIM_COUNT GENMASK(27, 16)
#define RX_MPDU_START_INFO12_AMPDU_FLAG BIT(28)
#define RX_MPDU_START_INFO12_BAR_FRAME BIT(29)
#define RX_MPDU_START_INFO12_RAW_MPDU BIT(30)
#define RX_MPDU_START_INFO13_MPDU_LEN GENMASK(13, 0)
#define RX_MPDU_START_INFO13_FIRST_MPDU BIT(14)
#define RX_MPDU_START_INFO13_MCAST_BCAST BIT(15)
#define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND BIT(16)
#define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT BIT(17)
#define RX_MPDU_START_INFO13_POWER_MGMT BIT(18)
#define RX_MPDU_START_INFO13_NON_QOS BIT(19)
#define RX_MPDU_START_INFO13_NULL_DATA BIT(20)
#define RX_MPDU_START_INFO13_MGMT_TYPE BIT(21)
#define RX_MPDU_START_INFO13_CTRL_TYPE BIT(22)
#define RX_MPDU_START_INFO13_MORE_DATA BIT(23)
#define RX_MPDU_START_INFO13_EOSP BIT(24)
#define RX_MPDU_START_INFO13_FRAGMENT BIT(25)
#define RX_MPDU_START_INFO13_ORDER BIT(26)
#define RX_MPDU_START_INFO13_UAPSD_TRIGGER BIT(27)
#define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED BIT(28)
#define RX_MPDU_START_INFO13_DIRECTED BIT(29)
#define RX_MPDU_START_INFO13_AMSDU_PRESENT BIT(30)
struct rx_mpdu_start_qcn9074 {
__le32 info7;
__le32 reo_queue_desc_lo;
__le32 info8;
__le32 pn[4];
__le32 info9;
__le32 peer_meta_data;
__le16 info10;
__le16 phy_ppdu_id;
__le16 ast_index;
__le16 sw_peer_id;
__le32 info11;
__le32 info12;
__le32 info13;
__le16 frame_ctrl;
__le16 duration;
u8 addr1[ETH_ALEN];
u8 addr2[ETH_ALEN];
u8 addr3[ETH_ALEN];
__le16 seq_ctrl;
u8 addr4[ETH_ALEN];
__le16 qos_ctrl;
__le32 ht_ctrl;
} __packed;
/* rx_mpdu_start
*
* rxpcu_mpdu_filter_in_category
@@ -672,7 +778,7 @@ enum rx_msdu_start_reception_type {
#define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21)
#define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24)
struct rx_msdu_start {
struct rx_msdu_start_ipq8074 {
__le16 info0;
__le16 phy_ppdu_id;
__le32 info1;
@@ -684,6 +790,20 @@ struct rx_msdu_start {
__le32 phy_meta_data;
} __packed;
struct rx_msdu_start_qcn9074 {
__le16 info0;
__le16 phy_ppdu_id;
__le32 info1;
__le32 info2;
__le32 toeplitz_hash;
__le32 flow_id_toeplitz;
__le32 info3;
__le32 ppdu_start_timestamp;
__le32 phy_meta_data;
__le16 vlan_ctag_c1;
__le16 vlan_stag_c1;
} __packed;
/* rx_msdu_start
*
* rxpcu_mpdu_filter_in_category
@@ -894,7 +1014,7 @@ struct rx_msdu_start {
#define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1)
#define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6)
struct rx_msdu_end {
struct rx_msdu_end_ipq8074 {
__le16 info0;
__le16 phy_ppdu_id;
__le16 ip_hdr_cksum;
@@ -917,6 +1037,58 @@ struct rx_msdu_end {
__le16 sa_sw_peer_id;
} __packed;
#define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0)
#define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0)
#define RX_MSDU_END_INFO2_SA_OFFSET GENMASK(11, 6)
#define RX_MSDU_END_INFO2_DA_OFFSET_VALID BIT(12)
#define RX_MSDU_END_INFO2_SA_OFFSET_VALID BIT(13)
#define RX_MSDU_END_INFO2_L3_TYPE GENMASK(31, 16)
#define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT BIT(0)
#define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT BIT(1)
#define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR BIT(2)
#define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT BIT(3)
#define RX_MSDU_END_INFO4_FLOW_IDX_INVALID BIT(4)
#define RX_MSDU_END_INFO4_WIFI_PARSER_ERR BIT(5)
#define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR BIT(6)
#define RX_MSDU_END_INFO4_SA_IS_VALID BIT(7)
#define RX_MSDU_END_INFO4_DA_IS_VALID BIT(8)
#define RX_MSDU_END_INFO4_DA_IS_MCBC BIT(9)
#define RX_MSDU_END_INFO4_L3_HDR_PADDING GENMASK(11, 10)
#define RX_MSDU_END_INFO4_FIRST_MSDU BIT(12)
#define RX_MSDU_END_INFO4_LAST_MSDU BIT(13)
#define RX_MSDU_END_INFO6_AGGR_COUNT GENMASK(7, 0)
#define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN BIT(8)
#define RX_MSDU_END_INFO6_FISA_TIMEOUT BIT(9)
struct rx_msdu_end_qcn9074 {
__le16 info0;
__le16 phy_ppdu_id;
__le16 ip_hdr_cksum;
__le16 mpdu_length_info;
__le32 info1;
__le32 rule_indication[2];
__le32 info2;
__le32 ipv6_options_crc;
__le32 tcp_seq_num;
__le32 tcp_ack_num;
__le16 info3;
__le16 window_size;
__le16 tcp_udp_cksum;
__le16 info4;
__le16 sa_idx;
__le16 da_idx;
__le32 info5;
__le32 fse_metadata;
__le16 cce_metadata;
__le16 sa_sw_peer_id;
__le32 info6;
__le16 cum_l4_cksum;
__le16 cum_ip_length;
} __packed;
/* rx_msdu_end
*
* rxpcu_mpdu_filter_in_category
@@ -1190,16 +1362,16 @@ struct rx_mpdu_end {
#define HAL_RX_DESC_HDR_STATUS_LEN 120
struct hal_rx_desc {
struct hal_rx_desc_ipq8074 {
__le32 msdu_end_tag;
struct rx_msdu_end msdu_end;
struct rx_msdu_end_ipq8074 msdu_end;
__le32 rx_attn_tag;
struct rx_attention attention;
__le32 msdu_start_tag;
struct rx_msdu_start msdu_start;
struct rx_msdu_start_ipq8074 msdu_start;
u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
__le32 mpdu_start_tag;
struct rx_mpdu_start mpdu_start;
struct rx_mpdu_start_ipq8074 mpdu_start;
__le32 mpdu_end_tag;
struct rx_mpdu_end mpdu_end;
u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
@@ -1209,6 +1381,32 @@ struct hal_rx_desc {
u8 msdu_payload[0];
} __packed;
struct hal_rx_desc_qcn9074 {
__le32 msdu_end_tag;
struct rx_msdu_end_qcn9074 msdu_end;
__le32 rx_attn_tag;
struct rx_attention attention;
__le32 msdu_start_tag;
struct rx_msdu_start_qcn9074 msdu_start;
u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
__le32 mpdu_start_tag;
struct rx_mpdu_start_qcn9074 mpdu_start;
__le32 mpdu_end_tag;
struct rx_mpdu_end mpdu_end;
u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
__le32 hdr_status_tag;
__le32 phy_ppdu_id;
u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
u8 msdu_payload[0];
} __packed;
struct hal_rx_desc {
union {
struct hal_rx_desc_ipq8074 ipq8074;
struct hal_rx_desc_qcn9074 qcn9074;
} u;
} __packed;
#define HAL_RX_RU_ALLOC_TYPE_MAX 6
#define RU_26 1
#define RU_52 2