dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible

Add the 'hpe,gsc-dwcmshc' compatible string for the HPE GSC (ARM64
Cortex-A53) BMC SoC eMMC controller.

The HPE GSC requires access to the MSHCCS register in the SoC system
register block to configure SCG sync disable for HS200 RX delay-line
phase selection.  The required 'hpe,gxp-sysreg' property takes a
phandle to the existing 'hpe,gxp-sysreg' syscon and the MSHCCS
register offset within that block.

The HPE GSC eMMC interface only exposes a single 'core' clock (no
bus clock), so clocks/clock-names are constrained to a single item.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Nick Hawkins
2026-03-16 10:01:14 -05:00
committed by Ulf Hansson
parent 3f1628baa5
commit e65a413a2d

View File

@@ -23,6 +23,7 @@ properties:
- const: sophgo,sg2044-dwcmshc
- const: sophgo,sg2042-dwcmshc
- enum:
- hpe,gsc-dwcmshc
- rockchip,rk3568-dwcmshc
- rockchip,rk3588-dwcmshc
- snps,dwcmshc-sdhci
@@ -79,6 +80,17 @@ properties:
description: Specifies the drive impedance in Ohm.
enum: [33, 40, 50, 66, 100]
hpe,gxp-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to HPE GXP SoC system register block (syscon)
- description: offset of the MSHCCS register within the syscon block
description:
Phandle to the HPE GXP SoC system register block (syscon) and
offset of the MSHCCS register used to configure clock
synchronisation for HS200 tuning.
required:
- compatible
- reg
@@ -89,6 +101,26 @@ required:
allOf:
- $ref: mmc-controller.yaml#
- if:
properties:
compatible:
contains:
const: hpe,gsc-dwcmshc
then:
properties:
clocks:
items:
- description: core clock
clock-names:
items:
- const: core
required:
- hpe,gxp-sysreg
else:
properties:
hpe,gxp-sysreg: false
- if:
properties:
compatible: