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drm/amdkfd: Set TG_CHUNK_SIZE for GC 9.4.3

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On GC 9.4.3, DW 41 in MQD is repurposed as compute_tg_chunk_size
for cooperative dispatch. When it's a AQL queue, set compute_tg_chunk_size
as 1 to spread work groups evenly among XCCs. If it's PM4 queue, unset
compute_tg_chunk_size to disable cooperative mode.

v3: set compute_tg_chunk_size as 1 instead of #CUs per XCC
v2: set compute_tg_chunk_size as #CUs per XCC instead of total wave
slots per XCC

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Sean Keely <Sean.Keely@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Amber Lin
2021-12-06 17:22:42 +08:00
committed by Alex Deucher
parent 1d44ff3d7a
commit e5a6702e51
1 changed files with 15 additions and 0 deletions
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15
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
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@@ -135,6 +135,7 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
{
uint64_t addr;
struct v9_mqd *m;
struct amdgpu_device *adev = (struct amdgpu_device *)mm->dev->adev;
m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr;
addr = mqd_mem_obj->gpu_addr;
@@ -167,6 +168,20 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
if (q->format == KFD_QUEUE_FORMAT_AQL) {
m->cp_hqd_aql_control =
1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) {
/* On GC 9.4.3, DW 41 is re-purposed as
* compute_tg_chunk_size.
* TODO: review this setting when active CUs in the
* partition play a role
*/
m->compute_static_thread_mgmt_se6 = 1;
}
} else {
/* PM4 queue */
if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) {
m->compute_static_thread_mgmt_se6 = 0;
/* TODO: program pm4_target_xcc */
}
}
if (q->tba_addr) {