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arm64: dts: ti: k3-am642-phyboard-electra: Add PEB-C-010 Overlay
The PEB-C-010 expansion board adds two extra 1Gbps ethernet ports to the phyBOARD-Electra-AM64x. Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://patch.msgid.link/20250910141716.2133707-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Garrett Giordano
committed by
Nishanth Menon
Nishanth Menon
parent
e402a3f1d9
commit
e53fbf955e
@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-peb-c-010.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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@@ -208,6 +209,8 @@ k3-am642-phyboard-electra-pcie-usb2-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo
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k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo
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k3-am642-phyboard-electra-peb-c-010-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-peb-c-010.dtbo
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k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
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k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
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158
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
Normal file
158
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
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@@ -0,0 +1,158 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Copyright (C) 2025 PHYTEC America LLC
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* Author: Garrett Giordano <ggiordano@phytec.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/net/ti-dp83869.h>
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#include "k3-pinctrl.h"
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&{/} {
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aliases {
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ethernet3 = "/icssg1-ethernet/ethernet-ports/port@0";
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ethernet4 = "/icssg1-ethernet/ethernet-ports/port@1";
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};
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icssg1-ethernet {
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compatible = "ti,am642-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>;
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dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
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<&main_pktdma 0xc201 15>, /* egress slice 0 */
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<&main_pktdma 0xc202 15>, /* egress slice 0 */
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<&main_pktdma 0xc203 15>, /* egress slice 0 */
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<&main_pktdma 0xc204 15>, /* egress slice 1 */
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<&main_pktdma 0xc205 15>, /* egress slice 1 */
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<&main_pktdma 0xc206 15>, /* egress slice 1 */
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<&main_pktdma 0xc207 15>, /* egress slice 1 */
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<&main_pktdma 0x4200 15>, /* ingress slice 0 */
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<&main_pktdma 0x4201 15>, /* ingress slice 1 */
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<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
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<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1",
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"rxmgm0", "rxmgm1";
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firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
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interrupt-parent = <&icssg1_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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sram = <&oc_sram>;
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ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
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ti,mii-g-rt = <&icssg1_mii_g_rt>;
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ti,mii-rt = <&icssg1_mii_rt>;
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ti,pa-stats = <&icssg1_pa_stats>;
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ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
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ti,pruss-gp-mux-sel = <2>, /* MII mode */
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<2>,
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<2>,
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<2>, /* MII mode */
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<2>,
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<2>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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icssg1_emac0: port@0 {
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reg = <0>;
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phy-handle = <&icssg1_phy1>;
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phy-mode = "rgmii-id";
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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ti,syscon-rgmii-delay = <&main_conf 0x4110>;
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};
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icssg1_emac1: port@1 {
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reg = <1>;
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phy-handle = <&icssg1_phy2>;
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phy-mode = "rgmii-id";
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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ti,syscon-rgmii-delay = <&main_conf 0x4114>;
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};
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};
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};
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};
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&main_pmx0 {
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icssg1_mdio_pins_default: icssg1-mdio-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
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AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
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>;
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};
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icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
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AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
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AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
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AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
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AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
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AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
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AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
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AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
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AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
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AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
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AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
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AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
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>;
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};
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icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
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AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
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AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
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AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
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AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
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AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
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AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */
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AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */
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AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */
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AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */
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AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */
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AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
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>;
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};
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};
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&icssg1_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&icssg1_mdio_pins_default>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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icssg1_phy1: ethernet-phy@1 {
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reg = <0x1>;
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rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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ti,min-output-impedance;
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};
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icssg1_phy2: ethernet-phy@2 {
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reg = <0x2>;
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rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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ti,min-output-impedance;
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};
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};
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