mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-12 17:26:47 -04:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: qcom: use defines for interrupts

Browse Source 
Replace hard-coded interrupt parts (GIC, flags) with standard defines
for readability.  No changes in resulting DTBs.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240605154605.149051-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2024-06-05 17:46:05 +02:00
committed by Bjorn Andersson
parent ba5d9a91f8
commit e502de5d40
4 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@@ -1093,10 +1093,10 @@ gmu_sram: gmu-sram@0 {
timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 0xff08>,
<GIC_PPI 3 0xff08>,
<GIC_PPI 4 0xff08>,
<GIC_PPI 1 0xff08>;
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
vph_pwr: vph-pwr-regulator {

8
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@@ -1531,10 +1531,10 @@ pcie@0 {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 0xff08>,
<GIC_PPI 3 0xff08>,
<GIC_PPI 4 0xff08>,
<GIC_PPI 1 0xff08>;
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
smp2p-adsp {

8
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@@ -2601,10 +2601,10 @@ gpu_alert0: trip-point0 {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 0xf08>,
<GIC_PPI 2 0xf08>,
<GIC_PPI 3 0xf08>,
<GIC_PPI 0 0xf08>;
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

8
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@@ -1588,10 +1588,10 @@ intc: interrupt-controller@f200000 {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 0xf08
GIC_PPI 2 0xf08
GIC_PPI 3 0xf08
GIC_PPI 0 0xf08>;
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};