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mlxsw: reg: Add ingress RIF related fields to SFMR register

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SFMR register creates and configures FIDs. As preparation for unified
bridge model, add some required fields for future use.

On ingress, after ingress ACL, a packet needs to be classified to a FID.
The key for this lookup can be one of:
1. VID. When port is not in virtual mode.
2. {RQ, VID}. When port is in virtual mode.
3. FID. When FID was set by ingress ACL.
   For example, via VR_AND_FID_ACTION.

Since RITR no longer performs ingress configuration, the ingress RIF for
the last entry type needs to be set via new fields in SFMR - 'irif_v'
and 'irif'.

Add the two mentioned fields for future use.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Cohen
2022-06-19 13:29:10 +03:00
committed by David S. Miller
parent 02d23c9544
commit e459466a26
1 changed files with 20 additions and 0 deletions
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20
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@@ -1818,6 +1818,26 @@ MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
*/
MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
/* reg_sfmr_irif_v
* Ingress RIF valid.
* 0 - Ingress RIF is not valid, no ingress RIF assigned.
* 1 - Ingress RIF valid.
* Must not be set for a non valid RIF.
* Access: RW
*
* Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
/* reg_sfmr_irif
* Ingress RIF (Router Interface).
* Range is 0..cap_max_router_interfaces-1.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and when irif_v=0.
*/
MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
static inline void mlxsw_reg_sfmr_pack(char *payload,
enum mlxsw_reg_sfmr_op op, u16 fid,
u16 fid_offset)