mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-16 04:21:09 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED

Browse Source 
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655384/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-14-3b2085a07884@oss.qualcomm.com
This commit is contained in:
Dmitry Baryshkov
2025-05-22 22:03:33 +03:00
committed by Dmitry Baryshkov
parent 19bcbadf92
commit e432d2e154
3 changed files with 2 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@@ -105,8 +105,7 @@
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_STATUS_SUPPORTED))
(BIT(DPU_INTF_INPUT_CTRL))
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@@ -143,12 +143,10 @@ enum {
* INTF sub-blocks
* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
* pixel data arrives to this INTF
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
};

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
View File

@@ -308,9 +308,8 @@ static void dpu_hw_intf_get_status(
struct dpu_hw_intf_status *s)
{
struct dpu_hw_blk_reg_map *c = &intf->hw;
unsigned long cap = intf->cap->features;
if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
if (intf->mdss_ver->core_major_ver >= 5)
s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
else
s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);