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drm/amd/display: Remove useless assignments

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[WHAT & HOW]
"split_pipe" are assigned to test_pipe and then immediately are updated
to other values. The same also applies to "status" as well.

Similarly, "id", "dwb" and "unused_dpps" are assigned but the functions
immediately return, and thus they have no effects.

As a results, the assignments removed.

This fixes 5 UNUSED_VALUE issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung
2024-09-30 11:29:02 -06:00
committed by Alex Deucher
parent 9237c9504b
commit e421808cbe
6 changed files with 0 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
View File

@@ -209,8 +209,6 @@ static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrappe
p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1;
if (odms_needed <= unused_dpps) {
unused_dpps -= odms_needed;
if (odms_needed == 1) {
p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_2to1;
optimization_done = true;

1
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
View File

@@ -443,7 +443,6 @@ struct gpio *dal_gpio_create_irq(
case GPIO_ID_GPIO_PAD:
break;
default:
id = GPIO_ID_HPD;
ASSERT_CRITICAL(false);
return NULL;
}

1
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@@ -3453,7 +3453,6 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
r2 = test_pipe->plane_res.scl_data.recout;
r2_r = r2.x + r2.width;
r2_b = r2.y + r2.height;
split_pipe = test_pipe;
/**
* There is another half plane on same layer because of

1
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
View File

@@ -486,7 +486,6 @@ bool dcn30_mmhubbub_warmup(
}
/*following is the original: warmup each DWB's mcif buffer*/
for (i = 0; i < num_dwb; i++) {
dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
/*warmup is for VM mode only*/
if (wb_info[i].mcif_buf_params.p_vmid == 0)

1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@@ -1068,7 +1068,6 @@ static bool dcn401_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
r2 = test_pipe->plane_res.scl_data.recout;
r2_r = r2.x + r2.width;
r2_b = r2.y + r2.height;
split_pipe = test_pipe;
/**
* There is another half plane on same layer because of

1
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
View File

@@ -412,7 +412,6 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
/* 5. check CR done*/
if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
status = LINK_TRAINING_SUCCESS;
break;
}