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riscv/runtime-const: Introduce runtime_const_mask_32()
Futex hash computation requires a mask operation with read-only after init data that will be converted to a runtime constant in the subsequent commit. Introduce runtime_const_mask_32 to further optimize the mask operation in the futex hash computation hot path. Since all the current use-cases are of the form GENMASK(n, 0), with n > 0, following sequence: srli a0, a1, imm slli a0, a0, imm is used for RISC-V where imm = (31 - width) to improve instruction density and performance. "The RISC-V Instruction Set Manual, Volume I - Unprivileged Architecture" [1] Sec. 2.4.1 "Integer Register-Immediate Instructions" notes the immediate shift for SRLI and SLLI are 5 bits wide starting at bit #10. __runtime_fixup_shift() is reused to patch the immediate shifts for the two instructions. If a future use case arises that needs to tackle arbitrary mask, consider using: lui a0, 0x12346 # upper; +0x800 then >>12 for correct rounding addi a0, a0, 0x678 # lower 12 bits to patch the 32-bit mask in the asm block and return "__ret & (val)" from runtime_const_mask_32() which allows compiler to further optimize the logical and operation. __runtime_fixup_ptr() already patches a lui + addi sequence which can be reused when the need arises. A possible implementation for this alternate scheme can be found at [2]. Suggested-by: Samuel Holland <samuel.holland@sifive.com> Suggested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Assisted-by: Claude:claude-sonnet-4-5 Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Link: https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf [1] Link: https://lore.kernel.org/lkml/20260430094730.31624-6-kprateek.nayak@amd.com/ [2] Link: https://patch.msgid.link/20260728052540.4728-6-kprateek.nayak@amd.com
This commit is contained in:
committed by
Peter Zijlstra
parent
ee10b10281
commit
e412c77541
@@ -34,6 +34,7 @@
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#define SZREG __REG_SEL(8, 4)
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#define LGREG __REG_SEL(3, 2)
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#define SRLI __REG_SEL(srliw, srli)
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#define SLLI __REG_SEL(slliw, slli)
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#if __SIZEOF_POINTER__ == 8
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#ifdef __ASSEMBLER__
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@@ -159,6 +159,23 @@
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__ret; \
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})
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#define runtime_const_mask_32(val, sym) \
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({ \
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u32 __ret; \
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asm_inline(".option push\n\t" \
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".option norvc\n\t" \
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"1:\t" \
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SLLI " %[__ret],%[__val],12\n\t" \
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SRLI " %[__ret],%[__ret],12\n\t" \
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".option pop\n\t" \
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".pushsection runtime_mask_" #sym ",\"a\"\n\t" \
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".long 1b - .\n\t" \
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".popsection" \
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: [__ret] "=r" (__ret) \
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: [__val] "r" (val)); \
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__ret; \
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})
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#define runtime_const_init(type, sym) do { \
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extern s32 __start_runtime_##type##_##sym[]; \
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extern s32 __stop_runtime_##type##_##sym[]; \
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@@ -262,6 +279,33 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val)
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mutex_unlock(&text_mutex);
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}
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static inline void __runtime_fixup_mask(void *where, unsigned long val)
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{
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unsigned int width = (val) ? __fls(val) + 1 : 0;
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/*
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* XXX: Current implementation only supports patching masks of
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* form GENMASK(width, 0) (width >= 0) using a SRLI + SLLI
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* sequence instead of LUI + ADDI + AND sequence to improve
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* performance, density, and covers all the current use-cases.
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*
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* When the need arises to support any generic mask, and this
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* BUG_ON() is tripped, consider using a:
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*
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* lui %[__ret], #imm16
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* addi %[__ret], #imm16
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*
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* sequence to load the 32bit const mask, and perform a logical
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* and outside the asm block before returning the result. Fixup
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* can simply reuse the existing __runtime_fixup_32() to patch
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* the LUI + ADDI sequence.
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*/
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BUG_ON(!val || width > 31 || (GENMASK(width - 1, 0) != val));
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__runtime_fixup_shift(where, 32 - width);
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__runtime_fixup_shift(where + 4, 32 - width);
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}
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static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),
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unsigned long val, s32 *start, s32 *end)
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{
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