mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-04-29 05:52:38 -04:00
Merge tag 'ti-k3-dt-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt
Devicetree changes for TI K3 platforms for v5.11 merge window: - Standardized usage of "disabled" only in board.dts files, #interrupt-cells warning fixups, node format error fixes - J721E: R5F support, MMC/SD UHS mode added - AM654: R5F support, dss marked coherent, drop unused dma-ring-reset-quirk property - J7200: ADC support, Mailbox, hwspinlock * tag 'ti-k3-dt-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (25 commits) arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes arm64: dts: ti: k3-j721e-main: Add output tap delay values arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes arm64: dts: ti: k3-j7200-main: Add hwspinlock node arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved" arm64: dts: ti: k3-am654-base-board: Fix up un-necessary status set to "okay" for USB arm64: dts: ti: am65/j721e: Fix up un-necessary status set to "okay" for crypto arm64: dts: ti: k3-j721e*: Cleanup disabled nodes at SoC dtsi level arm64: dts: ti: k3-am65*: Cleanup disabled nodes at SoC dtsi level arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores ... Link: https://lore.kernel.org/r/20201130174258.ljsiokkyr7x7tsbd@covenant Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -119,7 +119,6 @@ crypto: crypto@4e00000 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
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status = "okay";
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dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
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<&main_udmap 0x4001>;
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@@ -473,6 +472,7 @@ inta_main_udmass: interrupt-controller@33d00000 {
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interrupt-controller;
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interrupt-parent = <&intr_main_navss>;
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msi-controller;
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#interrupt-cells = <0>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <179>;
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ti,interrupt-ranges = <0 0 256>;
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@@ -612,7 +612,6 @@ ringacc: ringacc@3c000000 {
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <818>;
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <187>;
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msi-parent = <&inta_main_udmass>;
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@@ -770,8 +769,6 @@ mcasp0: mcasp@2b00000 {
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clocks = <&k3_clks 104 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcasp1: mcasp@2b10000 {
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@@ -789,8 +786,6 @@ mcasp1: mcasp@2b10000 {
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clocks = <&k3_clks 105 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcasp2: mcasp@2b20000 {
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@@ -808,8 +803,6 @@ mcasp2: mcasp@2b20000 {
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clocks = <&k3_clks 106 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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cal: cal@6f03000 {
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@@ -834,7 +827,7 @@ csi2_0: port@0 {
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};
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};
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dss: dss@04a00000 {
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dss: dss@4a00000 {
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compatible = "ti,am65x-dss";
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reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
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<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
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@@ -865,7 +858,7 @@ dss: dss@04a00000 {
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interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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dma-coherent;
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dss_ports: ports {
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#address-cells = <1>;
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@@ -2,7 +2,7 @@
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/*
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* Device Tree Source for AM6 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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@@ -135,7 +135,6 @@ mcu_ringacc: ringacc@2b800000 {
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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msi-parent = <&inta_main_udmass>;
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@@ -269,4 +268,44 @@ mcu_cpsw_cpts_mux: refclk-mux {
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};
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};
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};
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mcu_r5fss0: r5fss@41000000 {
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compatible = "ti,am654-r5fss";
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ti,cluster-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41000000 0x00 0x41000000 0x20000>,
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<0x41400000 0x00 0x41400000 0x20000>;
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power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
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mcu_r5fss0_core0: r5f@41000000 {
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compatible = "ti,am654-r5f";
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reg = <0x41000000 0x00008000>,
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<0x41010000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <159>;
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ti,sci-proc-ids = <0x01 0xff>;
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resets = <&k3_reset 159 1>;
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firmware-name = "am65x-mcu-r5f0_0-fw";
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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};
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mcu_r5fss0_core1: r5f@41400000 {
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compatible = "ti,am654-r5f";
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reg = <0x41400000 0x00008000>,
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<0x41410000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <245>;
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ti,sci-proc-ids = <0x02 0xff>;
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resets = <&k3_reset 245 1>;
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firmware-name = "am65x-mcu-r5f0_1-fw";
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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};
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};
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};
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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@@ -29,11 +29,42 @@ reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: secure-ddr@9e800000 {
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reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa0000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa0100000 0 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: ipc-memories@a2000000 {
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reg = <0x00 0xa2000000 0x00 0x00100000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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gpio-keys {
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@@ -211,7 +242,7 @@ AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "disabled";
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status = "reserved";
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};
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&main_uart0 {
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@@ -325,14 +356,6 @@ &sdhci1 {
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disable-wp;
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};
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&dwc3_1 {
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status = "okay";
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};
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&usb1_phy {
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status = "okay";
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};
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&usb1 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_pins_default>;
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@@ -441,6 +464,18 @@ &mailbox0_cluster11 {
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status = "disabled";
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};
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&mcu_r5fss0_core0 {
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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};
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&mcu_r5fss0_core1 {
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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@@ -486,3 +521,19 @@ &cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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&mcasp0 {
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status = "disabled";
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};
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&mcasp1 {
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status = "disabled";
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};
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&mcasp2 {
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status = "disabled";
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};
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&dss {
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status = "disabled";
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};
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@@ -43,13 +43,6 @@ J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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};
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&main_pmx0 {
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
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J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
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>;
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};
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
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@@ -79,7 +72,7 @@ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "disabled";
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status = "reserved";
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};
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&main_uart0 {
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@@ -89,7 +82,7 @@ &main_uart0 {
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&main_uart2 {
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/* MAIN UART 2 is used by R5F firmware */
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status = "disabled";
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status = "reserved";
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};
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&main_uart3 {
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@@ -146,10 +139,6 @@ &cpsw_port1 {
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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@@ -165,16 +154,26 @@ exp2: gpio@22 {
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};
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};
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|
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/*
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* The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
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* swapped on the CPB.
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*
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* main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
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* The i2c1 of the CPB (as it is labeled) is not connected to j7200.
|
||||
*/
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&main_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
|
||||
|
||||
exp4: gpio@20 {
|
||||
exp3: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
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reg = <0x20>;
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
|
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"UB926_LOCK", "UB926_PWR_SW_CNTRL",
|
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"UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -213,3 +212,9 @@ &usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -115,6 +115,120 @@ secure_proxy_main: mailbox@32c00000 {
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@30e00000 {
|
||||
compatible = "ti,am654-hwspinlock";
|
||||
reg = <0x00 0x30e00000 0x00 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mailbox0_cluster0: mailbox@31f80000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f80000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster1: mailbox@31f81000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f81000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@31f82000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f82000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@31f83000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f83000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster4: mailbox@31f84000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f84000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster5: mailbox@31f85000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f85000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster6: mailbox@31f86000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f86000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster7: mailbox@31f87000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f87000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster8: mailbox@31f88000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f88000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster9: mailbox@31f89000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f89000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster10: mailbox@31f8a000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8a000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster11: mailbox@31f8b000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8b000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
main_ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x00 0x3c000000 0x00 0x400000>,
|
||||
|
||||
@@ -270,4 +270,23 @@ hbmc: hyperbus@47034000 {
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
};
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
compatible = "ti,am3359-tscadc";
|
||||
reg = <0x00 0x40200000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 0 1>;
|
||||
assigned-clocks = <&k3_clks 0 3>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
dmas = <&main_udmap 0x7400>,
|
||||
<&main_udmap 0x7401>;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -48,6 +48,15 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
|
||||
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&hbmc {
|
||||
/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
|
||||
* appropriate node based on board detection
|
||||
@@ -63,3 +72,88 @@ flash@0,0 {
|
||||
reg = <0x00 0x00 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp_som: gpio@21 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
|
||||
"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
|
||||
"UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
|
||||
"GPIO_LIN_EN", "CAN_STB";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -67,6 +67,31 @@ vsys_5v0: fixedregulator-vsys5v0 {
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_alt: gpio-regulator-TLV71033 {
|
||||
compatible = "regulator-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
|
||||
regulator-name = "tlv71033";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_5v0>;
|
||||
gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
sound0: sound@0 {
|
||||
compatible = "ti,j721e-cpb-audio";
|
||||
model = "j721e-cpb";
|
||||
@@ -106,6 +131,12 @@ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usbss0_pins_default: main-usbss0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
|
||||
@@ -221,7 +252,7 @@ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
|
||||
|
||||
&wkup_uart0 {
|
||||
/* Wakeup UART is used by System firmware */
|
||||
status = "disabled";
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
@@ -295,6 +326,8 @@ &main_sdhci0 {
|
||||
|
||||
&main_sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv_alt>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
@@ -540,6 +573,46 @@ &dss {
|
||||
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp10 {
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
@@ -556,8 +629,10 @@ &mcasp10 {
|
||||
>;
|
||||
tx-num-evt = <0>;
|
||||
rx-num-evt = <0>;
|
||||
};
|
||||
|
||||
status = "okay";
|
||||
&mcasp11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
@@ -639,3 +714,7 @@ &pcie3_rc {
|
||||
&pcie3_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Device Tree Source for J721E SoC Family Main Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/mux/mux.h>
|
||||
@@ -148,6 +148,7 @@ main_udmass_inta: interrupt-controller@33d00000 {
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
msi-controller;
|
||||
#interrupt-cells = <0>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <209>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
@@ -345,8 +346,6 @@ main_crypto: crypto@4e00000 {
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
|
||||
<&main_udmap 0x4001>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
@@ -1081,7 +1080,11 @@ main_sdhci0: sdhci@4f80000 {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0xf>;
|
||||
ti,otap-del-sel-mmc-hs = <0xf>;
|
||||
ti,otap-del-sel-ddr52 = <0x5>;
|
||||
ti,otap-del-sel-hs200 = <0x6>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
dma-coherent;
|
||||
@@ -1096,11 +1099,15 @@ main_sdhci1: sdhci@4fb0000 {
|
||||
clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
|
||||
assigned-clocks = <&k3_clks 92 0>;
|
||||
assigned-clock-parents = <&k3_clks 92 1>;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
main_sdhci2: sdhci@4f98000 {
|
||||
@@ -1112,11 +1119,15 @@ main_sdhci2: sdhci@4f98000 {
|
||||
clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
|
||||
assigned-clocks = <&k3_clks 93 0>;
|
||||
assigned-clock-parents = <&k3_clks 93 1>;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
usbss0: cdns-usb@4104000 {
|
||||
@@ -1278,7 +1289,7 @@ ufs@4e84000 {
|
||||
};
|
||||
};
|
||||
|
||||
dss: dss@04a00000 {
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,j721e-dss";
|
||||
reg =
|
||||
<0x00 0x04a00000 0x00 0x10000>, /* common_m */
|
||||
@@ -1327,8 +1338,6 @@ dss: dss@04a00000 {
|
||||
"common_s1",
|
||||
"common_s2";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dss_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@@ -1350,8 +1359,6 @@ mcasp0: mcasp@2b00000 {
|
||||
clocks = <&k3_clks 174 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@2b10000 {
|
||||
@@ -1369,8 +1376,6 @@ mcasp1: mcasp@2b10000 {
|
||||
clocks = <&k3_clks 175 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp2: mcasp@2b20000 {
|
||||
@@ -1388,8 +1393,6 @@ mcasp2: mcasp@2b20000 {
|
||||
clocks = <&k3_clks 176 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp3: mcasp@2b30000 {
|
||||
@@ -1407,8 +1410,6 @@ mcasp3: mcasp@2b30000 {
|
||||
clocks = <&k3_clks 177 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp4: mcasp@2b40000 {
|
||||
@@ -1426,8 +1427,6 @@ mcasp4: mcasp@2b40000 {
|
||||
clocks = <&k3_clks 178 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp5: mcasp@2b50000 {
|
||||
@@ -1445,8 +1444,6 @@ mcasp5: mcasp@2b50000 {
|
||||
clocks = <&k3_clks 179 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp6: mcasp@2b60000 {
|
||||
@@ -1464,8 +1461,6 @@ mcasp6: mcasp@2b60000 {
|
||||
clocks = <&k3_clks 180 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp7: mcasp@2b70000 {
|
||||
@@ -1483,8 +1478,6 @@ mcasp7: mcasp@2b70000 {
|
||||
clocks = <&k3_clks 181 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp8: mcasp@2b80000 {
|
||||
@@ -1502,8 +1495,6 @@ mcasp8: mcasp@2b80000 {
|
||||
clocks = <&k3_clks 182 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp9: mcasp@2b90000 {
|
||||
@@ -1521,8 +1512,6 @@ mcasp9: mcasp@2b90000 {
|
||||
clocks = <&k3_clks 183 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp10: mcasp@2ba0000 {
|
||||
@@ -1540,8 +1529,6 @@ mcasp10: mcasp@2ba0000 {
|
||||
clocks = <&k3_clks 184 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcasp11: mcasp@2bb0000 {
|
||||
@@ -1559,8 +1546,6 @@ mcasp11: mcasp@2bb0000 {
|
||||
clocks = <&k3_clks 185 1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog0: watchdog@2200000 {
|
||||
@@ -1581,6 +1566,86 @@ watchdog1: watchdog@2210000 {
|
||||
assigned-clock-parents = <&k3_clks 253 5>;
|
||||
};
|
||||
|
||||
main_r5fss0: r5fss@5c00000 {
|
||||
compatible = "ti,j721e-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
||||
<0x5d00000 0x00 0x5d00000 0x20000>;
|
||||
power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
main_r5fss0_core0: r5f@5c00000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
reg = <0x5c00000 0x00008000>,
|
||||
<0x5c10000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <245>;
|
||||
ti,sci-proc-ids = <0x06 0xff>;
|
||||
resets = <&k3_reset 245 1>;
|
||||
firmware-name = "j7-main-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@5d00000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
reg = <0x5d00000 0x00008000>,
|
||||
<0x5d10000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <246>;
|
||||
ti,sci-proc-ids = <0x07 0xff>;
|
||||
resets = <&k3_reset 246 1>;
|
||||
firmware-name = "j7-main-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
main_r5fss1: r5fss@5e00000 {
|
||||
compatible = "ti,j721e-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
|
||||
<0x5f00000 0x00 0x5f00000 0x20000>;
|
||||
power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
main_r5fss1_core0: r5f@5e00000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
reg = <0x5e00000 0x00008000>,
|
||||
<0x5e10000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <247>;
|
||||
ti,sci-proc-ids = <0x08 0xff>;
|
||||
resets = <&k3_reset 247 1>;
|
||||
firmware-name = "j7-main-r5f1_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@5f00000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
reg = <0x5f00000 0x00008000>,
|
||||
<0x5f10000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <248>;
|
||||
ti,sci-proc-ids = <0x09 0xff>;
|
||||
resets = <&k3_reset 248 1>;
|
||||
firmware-name = "j7-main-r5f1_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
c66_0: dsp@4d80800000 {
|
||||
compatible = "ti,j721e-c66-dsp";
|
||||
reg = <0x4d 0x80800000 0x00 0x00048000>,
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
@@ -353,4 +353,44 @@ cpts@3d000 {
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_r5fss0: r5fss@41000000 {
|
||||
compatible = "ti,j721e-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
reg = <0x41000000 0x00008000>,
|
||||
<0x41010000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <250>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
resets = <&k3_reset 250 1>;
|
||||
firmware-name = "j7-mcu-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
reg = <0x41400000 0x00008000>,
|
||||
<0x41410000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <251>;
|
||||
ti,sci-proc-ids = <0x02 0xff>;
|
||||
resets = <&k3_reset 251 1>;
|
||||
firmware-name = "j7-mcu-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
@@ -26,6 +26,78 @@ secure_ddr: optee@9e800000 {
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
@@ -208,6 +280,42 @@ &mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c66_0 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
|
||||
Reference in New Issue
Block a user