arm64: dts: cix: Add OrangePi 6 Plus board support

OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC, built-in 12-core 64-bit
processor + NPU processor,integrated graphics processor, equipped with
16GB/32GB/64GB LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe
SSD,as well as SPI FLASH and TF slots to meet the needs of fast read/write
and high-capacity storage

Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Link: https://lore.kernel.org/r/20260110093406.2700505-3-gary.yang@cixtech.com
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
This commit is contained in:
Gary Yang
2026-01-10 17:34:06 +08:00
committed by Peter Chen
parent b53eb75f26
commit e39fadd6ef
2 changed files with 84 additions and 0 deletions

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@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb
dtb-$(CONFIG_ARCH_CIX) += sky1-xcp.dtb

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@@ -0,0 +1,83 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright 2025 Cix Technology Group Co., Ltd.
*
*/
/dts-v1/;
#include "sky1.dtsi"
#include "sky1-pinfunc.h"
/ {
model = "Xunlong,OrangePi 6 Plus";
compatible = "xunlong,orangepi-6-plus", "cix,sky1";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = &uart2;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x28000000>;
linux,cma-default;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hog-cfg {
pins {
pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>,
<CIX_PAD_GPIO145_FUNC_GPIO145>,
<CIX_PAD_GPIO146_FUNC_GPIO146>,
<CIX_PAD_GPIO147_FUNC_GPIO147>;
bias-pull-down;
drive-strength = <8>;
};
};
};
&iomuxc_s5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_s5>;
pinctrl_hog_s5: hog-s5-cfg {
pins {
pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>;
bias-pull-up;
drive-strength = <8>;
};
};
};
&pcie_x8_rc {
status = "okay";
};
&pcie_x2_rc {
status = "okay";
};
&pcie_x1_1_rc {
status = "okay";
};
&uart2 {
status = "okay";
};