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drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

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The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-2-prabhakar.mahadev-lad.rj@bp.renesas.com
This commit is contained in:
Lad Prabhakar
2025-06-09 23:56:22 +01:00
committed by Biju Das
parent 660942f244
commit e37a95d01d
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
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@@ -612,6 +612,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
if (mode->clock > 148500)
return MODE_CLOCK_HIGH;
if (mode->clock < 5803)
return MODE_CLOCK_LOW;
return MODE_OK;
}