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clk: qcom: videocc-glymur: Add video clock controller driver for Glymur
Add support for the video clock controller for video clients to be able to request for videocc clocks on Glymur platform. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-4-8f7d8b4d8edd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das
committed by
Bjorn Andersson
Bjorn Andersson
parent
1c8ce43e1e
commit
e2e0d2f3da
@@ -55,6 +55,15 @@ config CLK_GLYMUR_TCSRCC
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Support for the TCSR clock controller on Glymur devices.
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Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
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config CLK_GLYMUR_VIDEOCC
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tristate "Glymur Video Clock Controller"
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depends on ARM64 || COMPILE_TEST
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select CLK_GLYMUR_GCC
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help
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Support for the video clock controller on Glymur devices.
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Say Y if you want to support video devices and functionality such as
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video encode and decode.
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config CLK_KAANAPALI_CAMCC
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tristate "Kaanapali Camera Clock Controller"
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depends on ARM64 || COMPILE_TEST
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@@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
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obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o
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obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
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obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
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obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
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533
drivers/clk/qcom/videocc-glymur.c
Normal file
533
drivers/clk/qcom/videocc-glymur.c
Normal file
@@ -0,0 +1,533 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,glymur-videocc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO,
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DT_BI_TCXO_AO,
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DT_SLEEP_CLK,
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};
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enum {
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P_BI_TCXO,
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P_SLEEP_CLK,
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P_VIDEO_CC_PLL0_OUT_MAIN,
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};
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static const struct pll_vco taycan_eko_t_vco[] = {
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{ 249600000, 2500000000, 0 },
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};
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/* 720.0 MHz Configuration */
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static const struct alpha_pll_config video_cc_pll0_config = {
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.l = 0x25,
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.alpha = 0x8000,
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.config_ctl_val = 0x25c400e7,
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.config_ctl_hi_val = 0x0a8060e0,
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.config_ctl_hi1_val = 0xf51dea20,
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.user_ctl_val = 0x00000008,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll video_cc_pll0 = {
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.offset = 0x0,
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.config = &video_cc_pll0_config,
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.vco_table = taycan_eko_t_vco,
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.num_vco = ARRAY_SIZE(taycan_eko_t_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_taycan_eko_t_ops,
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},
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},
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data video_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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};
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static const struct parent_map video_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &video_cc_pll0.clkr.hw },
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};
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static const struct parent_map video_cc_parent_map_2[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data video_cc_parent_data_2[] = {
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{ .index = DT_SLEEP_CLK },
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};
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static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_ahb_clk_src = {
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.cmd_rcgr = 0x8018,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_ahb_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_ahb_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
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F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1965000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs0_clk_src = {
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.cmd_rcgr = 0x8000,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_1,
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.freq_tbl = ftbl_video_cc_mvs0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_clk_src",
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.parent_data = video_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
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F(32000, P_SLEEP_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_sleep_clk_src = {
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.cmd_rcgr = 0x8120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_2,
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.freq_tbl = ftbl_video_cc_sleep_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_sleep_clk_src",
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.parent_data = video_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 video_cc_xo_clk_src = {
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.cmd_rcgr = 0x80f8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_ahb_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_xo_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
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.reg = 0x809c,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
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.reg = 0x8060,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_div2_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
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.reg = 0x80d8,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_branch video_cc_mvs0_clk = {
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.halt_reg = 0x807c,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x807c,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x807c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_freerun_clk = {
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.halt_reg = 0x808c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x808c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_shift_clk = {
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.halt_reg = 0x8114,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x8114,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x8114,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_shift_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0c_clk = {
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.halt_reg = 0x804c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x804c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0c_freerun_clk = {
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.halt_reg = 0x805c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x805c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0c_shift_clk = {
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.halt_reg = 0x811c,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x811c,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x811c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_shift_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_clk = {
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.halt_reg = 0x80b8,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80b8,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80b8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs1_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_freerun_clk = {
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.halt_reg = 0x80c8,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x80c8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&video_cc_mvs1_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_shift_clk = {
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.halt_reg = 0x8118,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x8118,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x8118,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
|
||||
.name = "video_cc_mvs1_shift_clk",
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&video_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs0c_gdsc = {
|
||||
.gdscr = 0x8034,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs0c_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs0_gdsc = {
|
||||
.gdscr = 0x8068,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs0_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
.parent = &video_cc_mvs0c_gdsc.pd,
|
||||
};
|
||||
|
||||
static struct gdsc video_cc_mvs1_gdsc = {
|
||||
.gdscr = 0x80a4,
|
||||
.en_rest_wait_val = 0x2,
|
||||
.en_few_wait_val = 0x2,
|
||||
.clk_dis_wait_val = 0x6,
|
||||
.pd = {
|
||||
.name = "video_cc_mvs1_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
static struct clk_regmap *video_cc_glymur_clocks[] = {
|
||||
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
||||
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.clkr,
|
||||
[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
|
||||
[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
|
||||
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
|
||||
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
|
||||
[VIDEO_CC_MVS1_FREERUN_CLK] = &video_cc_mvs1_freerun_clk.clkr,
|
||||
[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr,
|
||||
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
|
||||
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
|
||||
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
|
||||
};
|
||||
|
||||
static struct gdsc *video_cc_glymur_gdscs[] = {
|
||||
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
|
||||
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
|
||||
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map video_cc_glymur_resets[] = {
|
||||
[VIDEO_CC_INTERFACE_BCR] = { 0x80dc },
|
||||
[VIDEO_CC_MVS0_BCR] = { 0x8064 },
|
||||
[VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 },
|
||||
[VIDEO_CC_MVS0C_BCR] = { 0x8030 },
|
||||
[VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x808c, 2 },
|
||||
[VIDEO_CC_MVS1_FREERUN_CLK_ARES] = { 0x80c8, 2 },
|
||||
[VIDEO_CC_MVS1_BCR] = { 0x80a0 },
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll *video_cc_glymur_plls[] = {
|
||||
&video_cc_pll0,
|
||||
};
|
||||
|
||||
static u32 video_cc_glymur_critical_cbcrs[] = {
|
||||
0x80e0, /* VIDEO_CC_AHB_CLK */
|
||||
0x8138, /* VIDEO_CC_SLEEP_CLK */
|
||||
0x8110, /* VIDEO_CC_XO_CLK */
|
||||
};
|
||||
|
||||
static const struct regmap_config video_cc_glymur_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9f54,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
|
||||
{
|
||||
/* Update CTRL_IN register */
|
||||
regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
|
||||
}
|
||||
|
||||
static struct qcom_cc_driver_data video_cc_glymur_driver_data = {
|
||||
.alpha_plls = video_cc_glymur_plls,
|
||||
.num_alpha_plls = ARRAY_SIZE(video_cc_glymur_plls),
|
||||
.clk_cbcrs = video_cc_glymur_critical_cbcrs,
|
||||
.num_clk_cbcrs = ARRAY_SIZE(video_cc_glymur_critical_cbcrs),
|
||||
.clk_regs_configure = clk_glymur_regs_configure,
|
||||
};
|
||||
|
||||
static struct qcom_cc_desc video_cc_glymur_desc = {
|
||||
.config = &video_cc_glymur_regmap_config,
|
||||
.clks = video_cc_glymur_clocks,
|
||||
.num_clks = ARRAY_SIZE(video_cc_glymur_clocks),
|
||||
.resets = video_cc_glymur_resets,
|
||||
.num_resets = ARRAY_SIZE(video_cc_glymur_resets),
|
||||
.gdscs = video_cc_glymur_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(video_cc_glymur_gdscs),
|
||||
.use_rpm = true,
|
||||
.driver_data = &video_cc_glymur_driver_data,
|
||||
};
|
||||
|
||||
static const struct of_device_id video_cc_glymur_match_table[] = {
|
||||
{ .compatible = "qcom,glymur-videocc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table);
|
||||
|
||||
static int video_cc_glymur_probe(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_cc_probe(pdev, &video_cc_glymur_desc);
|
||||
}
|
||||
|
||||
static struct platform_driver video_cc_glymur_driver = {
|
||||
.probe = video_cc_glymur_probe,
|
||||
.driver = {
|
||||
.name = "videocc-glymur",
|
||||
.of_match_table = video_cc_glymur_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(video_cc_glymur_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI VIDEOCC Glymur Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user