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riscv: dts: starfive - Add crypto and DMA node for JH7110

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Add hardware crypto module and dedicated dma controller node to StarFive
JH7110 SoC.

Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Jia Jie Ho
2023-08-08 22:15:57 +08:00
committed by Conor Dooley
parent b127dbf9e1
commit e2c07765e1
1 changed files with 27 additions and 0 deletions
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27
arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -821,6 +821,33 @@ watchdog@13070000 {
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
crypto: crypto@16000000 {
compatible = "starfive,jh7110-crypto";
reg = <0x0 0x16000000 0x0 0x4000>;
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
<&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
clock-names = "hclk", "ahb";
interrupts = <28>;
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
dmas = <&sdma 1 2>, <&sdma 0 2>;
dma-names = "tx", "rx";
};
sdma: dma-controller@16008000 {
compatible = "arm,pl080", "arm,primecell";
arm,primecell-periphid = <0x00041080>;
reg = <0x0 0x16008000 0x0 0x4000>;
interrupts = <29>;
clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
clock-names = "apb_pclk";
resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
lli-bus-interface-ahb1;
mem-bus-interface-ahb1;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
#dma-cells = <2>;
};
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;