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mmc: Merge branch fixes into next

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Merge the mmc fixes for v6.18-rc[n] into the next branch, to allow them to
get tested together with the new mmc changes that are targeted for v6.19.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ulf Hansson
2025-11-25 13:58:46 +01:00
parent b1f856b172 747528729c
commit e2bbd950eb
1 changed files with 17 additions and 12 deletions
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29
drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -352,6 +352,19 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
sdhci_adma_write_desc(host, desc, addr, len, cmd);
}
static void dwcmshc_reset(struct sdhci_host *host, u8 mask)
{
sdhci_reset(host, mask);
/* The dwcmshc does not comply with the SDHCI specification
* regarding the "Software Reset for CMD line should clear 'Command
* Complete' in the Normal Interrupt Status Register." Clear the bit
* here to compensate for this quirk.
*/
if (mask & SDHCI_RESET_CMD)
sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
}
static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -964,15 +977,7 @@ static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
u16 ctrl_2;
sdhci_reset(host, mask);
/* The T-Head 1520 SoC does not comply with the SDHCI specification
* regarding the "Software Reset for CMD line should clear 'Command
* Complete' in the Normal Interrupt Status Register." Clear the bit
* here to compensate for this quirk.
*/
if (mask & SDHCI_RESET_CMD)
sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
dwcmshc_reset(host, mask);
if (priv->flags & FLAG_IO_FIXED_1V8) {
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
@@ -1018,7 +1023,7 @@ static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
sdhci_reset(host, mask);
dwcmshc_reset(host, mask);
if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
@@ -1090,7 +1095,7 @@ static void cv18xx_sdhci_post_tuning(struct sdhci_host *host)
val |= SDHCI_INT_DATA_AVAIL;
sdhci_writel(host, val, SDHCI_INT_STATUS);
sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
}
static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
@@ -1637,7 +1642,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = {
.set_bus_width = sdhci_set_bus_width,
.set_uhs_signaling = dwcmshc_set_uhs_signaling,
.get_max_clock = dwcmshc_get_max_clock,
.reset = sdhci_reset,
.reset = dwcmshc_reset,
.adma_write_desc = dwcmshc_adma_write_desc,
.irq = dwcmshc_cqe_irq_handler,
};