mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-04 09:21:34 -04:00
Code Issues Packages Projects Releases Wiki Activity

ASoC: cs35l56: Update hibernate/wake sequences and

Browse Source 
Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>:

Update the hibernate and wake command sequences to meet the latest
datasheet specification and enable hibernation for I2C and SPI control
interfaces.

Richard Fitzgerald (1):
  ASoC: cs35l56: Enable low-power hibernation mode on SPI

Simon Trimmer (3):
  ASoC: cs35l56: Change hibernate sequence to use allow auto hibernate
  ASoC: cs35l56: Wake transactions need to be issued twice
  ASoC: cs35l56: Enable low-power hibernation mode on i2c

 include/sound/cs35l56.h           |  1 +
 sound/soc/codecs/cs35l56-i2c.c    |  1 +
 sound/soc/codecs/cs35l56-shared.c | 66 +++++++++++++++++++------------
 sound/soc/codecs/cs35l56-spi.c    |  1 +
 4 files changed, 43 insertions(+), 26 deletions(-)

--
2.30.2
This commit is contained in:
Mark Brown
2023-10-06 15:32:31 +01:00
parent 4b226f1542 634ed138d8
commit e22ece0f65
4 changed files with 43 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/sound/cs35l56.h
View File

@@ -243,6 +243,7 @@
#define CS35L56_HALO_STATE_POLL_US 1000
#define CS35L56_HALO_STATE_TIMEOUT_US 50000
#define CS35L56_RESET_PULSE_MIN_US 1100
#define CS35L56_WAKE_HOLD_TIME_US 1000
#define CS35L56_SDW1_PLAYBACK_PORT 1
#define CS35L56_SDW1_CAPTURE_PORT 3

1
sound/soc/codecs/cs35l56-i2c.c
View File

@@ -27,6 +27,7 @@ static int cs35l56_i2c_probe(struct i2c_client *client)
return -ENOMEM;
cs35l56->base.dev = dev;
cs35l56->base.can_hibernate = true;
i2c_set_clientdata(client, cs35l56);
cs35l56->base.regmap = devm_regmap_init_i2c(client, regmap_config);

66
sound/soc/codecs/cs35l56-shared.c
View File

@@ -439,13 +439,39 @@ EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
static const struct reg_sequence cs35l56_hibernate_seq[] = {
/* This must be the last register access */
REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW),
REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
};
static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
};
static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
{
/*
* Dummy transactions to trigger I2C/SPI auto-wake. Issue two
* transactions to meet the minimum required time from the rising edge
* to the last falling edge of wake.
*
* It uses bypassed write because we must wake the chip before
* disabling regmap cache-only.
*
* This can NAK on I2C which will terminate the write sequence so the
* single-write sequence is issued twice.
*/
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_hibernate_wake_seq,
ARRAY_SIZE(cs35l56_hibernate_wake_seq));
usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_hibernate_wake_seq,
ARRAY_SIZE(cs35l56_hibernate_wake_seq));
cs35l56_wait_control_port_ready();
}
int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
{
unsigned int val;
@@ -473,12 +499,6 @@ int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
return 0;
}
/*
* Enable auto-hibernate. If it is woken by some other wake source
* it will automatically return to hibernate.
*/
cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE);
/*
* Must enter cache-only first so there can't be any more register
* accesses other than the controlled hibernate sequence below.
@@ -506,17 +526,9 @@ int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_sou
if (!cs35l56_base->can_hibernate)
goto out_sync;
if (!is_soundwire) {
/*
* Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C.
* Must be done before releasing cache-only.
*/
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_hibernate_wake_seq,
ARRAY_SIZE(cs35l56_hibernate_wake_seq));
cs35l56_wait_control_port_ready();
}
/* Must be done before releasing cache-only */
if (!is_soundwire)
cs35l56_issue_wake_event(cs35l56_base);
out_sync:
regcache_cache_only(cs35l56_base->regmap, false);
@@ -545,11 +557,12 @@ int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_sou
return 0;
err:
regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
CS35L56_MBOX_CMD_HIBERNATE_NOW);
regcache_cache_only(cs35l56_base->regmap, true);
regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
cs35l56_hibernate_seq,
ARRAY_SIZE(cs35l56_hibernate_seq));
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
@@ -583,13 +596,14 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
unsigned int devid, revid, otpid, secured;
/*
* If the system is not using a reset_gpio then issue a
* dummy read to force a wakeup.
* When the system is not using a reset_gpio ensure the device is
* awake, otherwise the device has just been released from reset and
* the driver must wait for the control port to become usable.
*/
if (!cs35l56_base->reset_gpio)
regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid);
cs35l56_wait_control_port_ready();
cs35l56_issue_wake_event(cs35l56_base);
else
cs35l56_wait_control_port_ready();
/*
* The HALO_STATE register is in different locations on Ax and B0

1
sound/soc/codecs/cs35l56-spi.c
View File

@@ -32,6 +32,7 @@ static int cs35l56_spi_probe(struct spi_device *spi)
}
cs35l56->base.dev = &spi->dev;
cs35l56->base.can_hibernate = true;
ret = cs35l56_common_probe(cs35l56);
if (ret != 0)