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soc: qcom: ubwc: set min_acc length to 64 for all UBWC 1.0 targets
According to the documentation, the MAL should be set for all UBWC 1.0 targets, no matter what is the version of the UBWC decoders are present on the device. The helper comes from DPU / GPU world, where there was no separate bit to control MAL before UBWC 2.0. As the helper is now being used by other drivers too, correct the helper to return the correct MAL value (Iris doesn't support UBWC 1.0 devices for now, so there is no changes of the behaviour). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-22-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Bjorn Andersson
parent
9038810105
commit
e21d3b2e5c
@@ -75,14 +75,9 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
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return ret;
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}
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/*
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* This is the best guess, based on the MDSS driver, which worked so far.
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*/
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static inline bool qcom_ubwc_min_acc_length_64b(const struct qcom_ubwc_cfg_data *cfg)
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{
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return cfg->ubwc_enc_version == UBWC_1_0 &&
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(cfg->ubwc_dec_version == UBWC_2_0 ||
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cfg->ubwc_dec_version == UBWC_3_0);
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return cfg->ubwc_enc_version == UBWC_1_0;
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}
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static inline bool qcom_ubwc_macrotile_mode(const struct qcom_ubwc_cfg_data *cfg)
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