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drm/i915/dp: Update Comment for Valid DSC Slices per Line

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For some platforms, the maximum slices per DSC engine is 4, while for
others it is 2. Update the comment to reflect this and clarify that
the 'valid_dsc_slicecount' list represents the valid number of slices
per pipe.

Currently, we are working with 1, and 2 slices per DSC engine,
which works for all platforms. With this the number of slices per pipe
can be 1,2 or 4 with different slice & DSC engine configuration.

Add a #TODO for adding support for 4 slices per DSC engine where
supported.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-2-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal
2024-10-30 09:40:30 +05:30
parent 3c1d5ced18
commit e1faaca9d4
1 changed files with 8 additions and 2 deletions
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10
drivers/gpu/drm/i915/display/intel_dp.c
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@@ -109,8 +109,14 @@
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
/* With Single pipe configuration, HW is capable of supporting maximum
* of 4 slices per line.
/*
* With Single pipe configuration, HW is capable of supporting maximum of:
* 2 slices per line for ICL, BMG
* 4 slices per line for other platforms.
* For now consider a max of 2 slices per line, which works for all platforms.
* With this we can have max of 4 DSC Slices per pipe.
*
* #TODO Split this better to use 4 slices/dsc engine where supported.
*/
static const u8 valid_dsc_slicecount[] = {1, 2, 4};