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drm/panel: simple: Add Ampire AM-800480N3TZQW-00H

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Add support for the Ampire AM-800480N3TZQW-00H 5" WVGA TFT LCD panel.

Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260723-support-am-800480n3tzqw-00h-v1-2-6a4ae0575a19@bootlin.com
This commit is contained in:
Paul Louvel
2026-07-23 18:31:50 +02:00
committed by Neil Armstrong
parent 108a73346f
commit e1bde8ef0a
1 changed files with 33 additions and 0 deletions
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33
drivers/gpu/drm/panel/panel-simple.c
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@@ -912,6 +912,36 @@ static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
static const struct display_timing ampire_am_800480n3tzqw_00h_timing = {
.pixelclock = {23000000, 25000000, 27000000},
.hactive = { 800, 800, 800 },
.hfront_porch = { 4, 8, 48 },
.hback_porch = { 4, 8, 48 },
.hsync_len = { 2, 8, 8 },
.vactive = { 480, 480, 480 },
.vfront_porch = { 4, 8, 12 },
.vback_porch = { 4, 8, 12 },
.vsync_len = { 2, 4, 8 },
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
DISPLAY_FLAGS_SYNC_POSEDGE,
};
static const struct panel_desc ampire_am_800480n3tzqw_00h = {
.timings = &ampire_am_800480n3tzqw_00h_timing,
.num_timings = 1,
.bpc = 8,
.size = {
.width = 108,
.height = 65,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
.bus_flags = DRM_BUS_FLAG_DE_HIGH |
DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
static const struct panel_desc ampire_am800480r3tmqwa1h = {
.modes = &ampire_am800480r3tmqwa1h_mode,
.num_modes = 1,
@@ -5648,6 +5678,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "ampire,am-800480l1tmqw-t00h",
.data = &ampire_am_800480l1tmqw_t00h,
}, {
.compatible = "ampire,am-800480n3tzqw-00h",
.data = &ampire_am_800480n3tzqw_00h,
}, {
.compatible = "ampire,am800480r3tmqwa1h",
.data = &ampire_am800480r3tmqwa1h,