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clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic

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ma35d1_clk_pll_determine_rate() called ma35d1_pll_find_closest()
unconditionally before the switch statement, and then every case
branch overwrote pll_freq by reading the current hardware registers.
For CAPLL and DDRPLL this means find_closest() ran unnecessarily
(and incorrectly, since those PLLs are read-only) and its result
was silently discarded.

Fix by moving the find_closest() call inside the APLL/EPLL/VPLL
branch where it belongs.  Group CAPLL and DDRPLL together as
read-only PLLs that simply report their current rate; handle them
with an explicit if/else to keep the CAPLL (SMIC design) and DDRPLL
(standard design) paths distinct.

Fixes: 691521a367 ("clk: nuvoton: Add clock driver for ma35d1 clock controller")
Signed-off-by: Joey Lu <a0987203069@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Joey Lu
2026-05-21 09:42:20 +08:00
committed by Brian Masney
parent 26de5aed72
commit e1311954cb
1 changed files with 15 additions and 15 deletions
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30
drivers/clk/nuvoton/clk-ma35d1-pll.c
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@@ -255,32 +255,32 @@ static int ma35d1_clk_pll_determine_rate(struct clk_hw *hw,
if (req->best_parent_rate < PLL_FREF_MIN_FREQ || req->best_parent_rate > PLL_FREF_MAX_FREQ)
return -EINVAL;
ret = ma35d1_pll_find_closest(pll, req->rate, req->best_parent_rate,
reg_ctl, &pll_freq);
if (ret < 0)
return ret;
switch (pll->id) {
case CAPLL:
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], req->best_parent_rate);
req->rate = pll_freq;
return 0;
case DDRPLL:
/* Read-only PLLs: return current rate */
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
if (pll->id == CAPLL) {
pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], req->best_parent_rate);
} else {
reg_ctl[1] = readl_relaxed(pll->ctl1_base);
pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, req->best_parent_rate);
}
req->rate = pll_freq;
return 0;
case APLL:
case EPLL:
case VPLL:
reg_ctl[0] = readl_relaxed(pll->ctl0_base);
reg_ctl[1] = readl_relaxed(pll->ctl1_base);
pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, req->best_parent_rate);
/* Configurable PLLs: find closest achievable rate */
ret = ma35d1_pll_find_closest(pll, req->rate, req->best_parent_rate,
reg_ctl, &pll_freq);
if (ret < 0)
return ret;
req->rate = pll_freq;
return 0;
}
req->rate = 0;
return 0;
}