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arm64: dts: freescale: imx95-toradex-smarc: Add SER2 interface

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The Toradex SMARC iMX95 has four exposed serial interfaces, one of these
is SER2, which supports RTS/CTS.

Add UART support for SMARC SER2.

Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Franz Schnyder
2026-03-26 15:37:04 +01:00
committed by Frank Li
parent 5d20f1ccb3
commit e11598cbbb
2 changed files with 21 additions and 0 deletions
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5
arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts
View File

@@ -210,6 +210,11 @@ &lpuart3 {
status = "okay";
};
/* SMARC SER2 */
&lpuart6 {
status = "okay";
};
/* SMARC MDIO, shared between all ethernet ports */
&netc_emdio {
status = "okay";

16
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
View File

@@ -22,6 +22,7 @@ aliases {
rtc1 = &scmi_bbm;
serial0 = &lpuart2;
serial1 = &lpuart1;
serial2 = &lpuart6;
serial3 = &lpuart3;
};
@@ -615,6 +616,13 @@ &lpuart3 {
pinctrl-0 = <&pinctrl_uart3>;
};
/* SMARC SER2 */
&lpuart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
uart-has-rtscts;
};
&mu7 {
status = "okay";
};
@@ -1105,6 +1113,14 @@ pinctrl_uart3: uart3grp {
<IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */
};
/* SMARC SER2 */
pinctrl_uart6: uart6grp {
fsl,pins = <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* SMARC P139 - SER2_CTS# */
<IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>, /* SMARC P138 - SER2_RTS# */
<IMX95_PAD_GPIO_IO05__LPUART6_RX 0x31e>, /* SMARC P137 - SER2_RX */
<IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>; /* SMARC P136 - SER2_TX */
};
/* On-module eMMC */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */