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pinctrl: tegra20: register csus_mux clock

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Add csus_mux for further use as the csus clock parent, similar to how the
cdev1 and cdev2 muxes are utilized. Additionally, constify the cdev parent
name lists to resolve checkpatch warnings.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Svyatoslav Ryhel
2025-10-08 10:30:23 +03:00
committed by Linus Walleij
parent 005a325480
commit e1106d624c
1 changed files with 9 additions and 2 deletions
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11
drivers/pinctrl/tegra/pinctrl-tegra20.c
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@@ -2222,14 +2222,18 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
.drvtype_in_mux = false,
};
static const char *cdev1_parents[] = {
static const char * const cdev1_parents[] = {
"dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
};
static const char *cdev2_parents[] = {
static const char * const cdev2_parents[] = {
"dev2_osc_div", "hclk", "pclk", "pll_p_out4",
};
static const char * const csus_parents[] = {
"pll_c_out1", "pll_p_out2", "pll_p_out3", "vi_sensor",
};
static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
{
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
@@ -2239,6 +2243,9 @@ static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
clk_register_mux(NULL, "csus_mux", csus_parents, 4, 0,
pmx->regs[1] + 0x8, 6, 2, CLK_MUX_READ_ONLY, NULL);
}
static int tegra20_pinctrl_probe(struct platform_device *pdev)