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drm/amdgpu/gfx12: properly reference EOP interrupts for userqs

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Regardless of whether we disable kernel queues, we need
to take an extra reference to the pipe interrupts for
user queues to make sure they stay enabled in case we
disable them for kernel queues.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2025-04-13 10:19:24 -04:00
parent ac9984cee7
commit e10414cf2e
1 changed files with 6 additions and 3 deletions
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9
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
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@@ -3680,10 +3680,10 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
bool enable)
{
if (adev->gfx.disable_kq) {
unsigned int irq_type;
int m, p, r;
unsigned int irq_type;
int m, p, r;
if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
for (m = 0; m < adev->gfx.me.num_me; m++) {
for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
@@ -3697,7 +3697,9 @@ static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
return r;
}
}
}
if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
@@ -3714,6 +3716,7 @@ static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
}
}
}
return 0;
}