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drm/amdgpu: remove 128 NOP hack from vm_flush v2
With the padding raised to 256 DW that shouldn't be needed any more. v2: reduce estimation as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
c81b07e6bc
commit
e08c90a774
@@ -6249,10 +6249,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
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/* GFX8 emits 128 dw nop to prevent DE do vm_flush before CE finish CEIB */
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if (usepfp)
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amdgpu_ring_insert_nop(ring, 128);
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
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WRITE_DATA_DST_SEL(0)) |
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@@ -6381,7 +6377,7 @@ static unsigned gfx_v8_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
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5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
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6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */
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7 + /* gfx_v8_0_ring_emit_pipeline_sync */
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256 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
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128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
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2 + /* gfx_v8_ring_emit_sb */
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3; /* gfx_v8_ring_emit_cntxcntl */
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}
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