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drm/amd/display: allow 18 bit dp output on DCN3

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We need this to pass dp compliance.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nikola Cornij <nikola.cornij@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2020-05-05 14:32:33 -04:00
committed by Alex Deucher
parent d95c368ab8
commit e0457659f8
2 changed files with 1 additions and 15 deletions
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14
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@@ -2020,20 +2020,6 @@ static bool dcn30_internal_validate_bw(
dml_log_mode_support_params(&context->bw_ctx.dml);
/* TODO: Need to check calculated vlevel why that fails validation of below resolutions */
if (context->res_ctx.pipe_ctx[0].stream != NULL) {
if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
vlevel = 0;
if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
vlevel = 0;
if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
vlevel = 0;
if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
vlevel = 0;
if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
vlevel = 0;
}
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;

2
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
View File

@@ -3628,7 +3628,7 @@ static double TruncToValidBPP(
}
}
} else {
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||
(DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
return BPP_INVALID;
} else {