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Merge tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

Browse Source 
i.MX fixes for 6.17:

- Correct FlexCAN PHY settings on imx95-19x19-evk board (Haibo Chen)
- Add missing microSD slot supplies for DH electronics i.MX8M Plus
  boards (Marek Vasut)
- Fix assigned clocks for JPEG encoder node on i.MX95 (Marek Vasut)
- A couple of regulator setting fixes for imx8mp-tqma8mpql
  board (Markus Niebel)

* tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx95: Fix JPEG encoder node assigned clock
  arm64: dts: imx95-19x19-evk: correct the phy setting for flexcan1/2
  arm64: dts: imx8mp: Fix missing microSD slot vqmmc on Data Modul i.MX8M Plus eDM SBC
  arm64: dts: imx8mp: Fix missing microSD slot vqmmc on DH electronics i.MX8M Plus DHCOM
  arm64: dts: imx8mp-tqma8mpql: remove virtual 3.3V regulator
  arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off

Link: https://lore.kernel.org/r/aK6BuzIYwUBRU1GW@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-09-01 10:41:20 +02:00
parent 0aee6faf5b 37e5caa557
commit e019bbd8e4
7 changed files with 44 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
View File

@@ -555,6 +555,7 @@ &usdhc2 {
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&ldo5>;
bus-width = <4>;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@@ -609,6 +609,7 @@ &usdhc2 {
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&ldo5>;
bus-width = <4>;
status = "okay";
};

13
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
View File

@@ -467,6 +467,10 @@ &pwm4 {
status = "okay";
};
&reg_usdhc2_vqmmc {
status = "okay";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
@@ -876,8 +880,7 @@ pinctrl_usdhc2: usdhc2grp {
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -886,8 +889,7 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -896,8 +898,7 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

13
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@@ -604,6 +604,10 @@ &pwm3 {
status = "okay";
};
&reg_usdhc2_vqmmc {
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -983,8 +987,7 @@ pinctrl_usdhc2: usdhc2grp {
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -993,8 +996,7 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -1003,8 +1005,7 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

31
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
View File

@@ -16,13 +16,18 @@ memory@40000000 {
reg = <0x0 0x40000000 0 0x80000000>;
};
/* identical to buck4_reg, but should never change */
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
regulator-name = "V_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1>,
<3300000 0x0>;
vin-supply = <&ldo5_reg>;
status = "disabled";
};
};
@@ -173,17 +178,21 @@ at24c02: eeprom@53 {
read-only;
reg = <0x53>;
pagesize = <16>;
vcc-supply = <&reg_vcc3v3>;
vcc-supply = <&buck4_reg>;
};
m24c64: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&reg_vcc3v3>;
vcc-supply = <&buck4_reg>;
};
};
&usdhc2 {
vqmmc-supply = <&reg_usdhc2_vqmmc>;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@@ -193,7 +202,7 @@ &usdhc3 {
non-removable;
no-sd;
no-sdio;
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&buck4_reg>;
vqmmc-supply = <&buck5_reg>;
status = "okay";
};
@@ -233,6 +242,10 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>;
};
pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,

10
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@@ -80,17 +80,17 @@ linux_cma: linux,cma {
flexcan1_phy: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
max-bitrate = <1000000>;
max-bitrate = <8000000>;
enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_LOW>;
};
flexcan2_phy: can-phy1 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
max-bitrate = <1000000>;
enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>;
max-bitrate = <8000000>;
enable-gpios = <&i2c4_gpio_expander_21 4 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c4_gpio_expander_21 3 GPIO_ACTIVE_LOW>;
};
reg_vref_1v8: regulator-1p8v {

2
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@@ -1843,7 +1843,7 @@ jpegenc: jpegenc@4c550000 {
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX95_CLK_VPU>,
<&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>;
assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>;
assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>;
assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>;
power-domains = <&scmi_devpd IMX95_PD_VPU>;
};