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drm/amd/display: Disable MPC split by default on special asic
[WHY] All of pipes will be used when the MPC split enable on the dcn which just has 2 pipes. Then MPO enter will trigger the minimal transition which need programe dcn from 2 pipes MPC split to 2 pipes MPO. This action will cause lag if happen frequently. [HOW] Disable the MPC split for the platform which dcn resource is limited Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
b97089b88c
commit
dfa7a18303
@@ -65,7 +65,7 @@ static const struct dc_debug_options debug_defaults_drv = {
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.timing_trace = false,
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.clock_trace = true,
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.disable_pplib_clock_request = true,
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.pipe_split_policy = MPC_SPLIT_DYNAMIC,
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.pipe_split_policy = MPC_SPLIT_AVOID,
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.force_single_disp_pipe_split = false,
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.disable_dcc = DCC_ENABLE,
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.vsr_support = true,
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