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drm/i915/color: Fix step discontinuity in Pre-CSC Gamma LUT
Clamp Segment 2 to the last user-provided LUT entry value instead of hardcoding it to 1.0 (1 << 24) to fix a step discontinuity. Link: https://lore.kernel.org/intel-gfx/20260521180143.2143262-1-sean@poorly.run/ #v1 Link: https://lore.kernel.org/intel-gfx/20260525135730.1122696-2-sean@poorly.run/ #v2 Changes in v2: - Split out into separate patches for pre/post csc fixes - Dropped loop bounds fix in favor of [1] Changes in v3: - Fix stale commit message [1]- https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com Signed-off-by: Sean Paul <seanpaul@google.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20260528230817.2455072-2-sean@poorly.run
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@@ -3968,6 +3968,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
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enum plane_id plane = to_intel_plane(state->plane)->id;
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const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
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u32 i, lut_size;
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u32 lut_val = 1 << 24;
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if (icl_is_hdr_plane(display, plane)) {
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lut_size = 128;
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@@ -3978,7 +3979,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
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if (pre_csc_lut) {
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for (i = 0; i < lut_size; i++) {
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u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
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lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
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intel_de_write_dsb(display, dsb,
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PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
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@@ -3990,7 +3991,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
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do {
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intel_de_write_dsb(display, dsb,
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PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
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(1 << 24));
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lut_val);
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} while (i++ < 130);
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} else {
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for (i = 0; i < lut_size; i++) {
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