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arm64: dts: exynosautov920: Add DMA nodes

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ExynosAutov920 SoC has 7 DMA controllers. Two secure DMAC
(SPDMA0 & SPDMA1) and five non-secure DMAC (PDMA0 to PDMA4).
Add the required dt nodes for the same.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Faraz Ata <faraz.ata@samsung.com>
Link: https://lore.kernel.org/r/20241212115709.1724-1-faraz.ata@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Faraz Ata
2024-12-12 17:27:05 +05:30
committed by Krzysztof Kozlowski
parent 8749e19c13
commit de7a4e0105
1 changed files with 63 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

63
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
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@@ -213,6 +213,69 @@ gic: interrupt-controller@10400000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
spdma0: dma-controller@10180000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10180000 0x1000>;
interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
spdma1: dma-controller@10190000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10190000 0x1000>;
interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
pdma0: dma-controller@101a0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x101a0000 0x1000>;
interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
pdma1: dma-controller@101b0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x101b0000 0x1000>;
interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
pdma2: dma-controller@101c0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x101c0000 0x1000>;
interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
pdma3: dma-controller@101d0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x101d0000 0x1000>;
interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
pdma4: dma-controller@101e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x101e0000 0x1000>;
interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
cmu_peric0: clock-controller@10800000 {
compatible = "samsung,exynosautov920-cmu-peric0";
reg = <0x10800000 0x8000>;