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drm/i915: pass dev_priv explicitly to PIPE_DATA_M2

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_DATA_M2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1fda9b8cd446727845089844a1c8eeb5c8ae7b5a.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2024-06-04 18:26:10 +03:00
parent 12967c4f21
commit ddbdeb6c59
3 changed files with 9 additions and 7 deletions
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6
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -2660,7 +2660,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
return;
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
PIPE_DATA_M2(dev_priv, transcoder),
PIPE_DATA_N2(transcoder),
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
@@ -3357,7 +3358,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
return;
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
PIPE_DATA_M2(dev_priv, transcoder),
PIPE_DATA_N2(transcoder),
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}

2
drivers/gpu/drm/i915/i915_reg.h
View File

@@ -2300,7 +2300,7 @@
#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
#define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
#define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
#define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)

8
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@@ -268,7 +268,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
@@ -276,7 +276,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
@@ -284,7 +284,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
@@ -292,7 +292,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));