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arm64: dts: imx8mp: add cpuidle state "cpu-pd-wait"

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So far, only WFI is supported on i.MX8mp platform. Add support for
deeper cpuidle state "cpu-pd-wait" that would allow for better power
usage during runtime. This is a port from NXP downstream kernel.

Signed-off-by: Catalin Popescu <catalin.popescu@leica-geosystems.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Catalin Popescu
2024-10-07 15:44:24 +02:00
committed by Shawn Guo
parent 4a0dc71f7b
commit dda1bc1d8a
1 changed files with 18 additions and 0 deletions
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18
arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@@ -47,6 +47,20 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -65,6 +79,7 @@ A53_0: cpu@0 {
nvmem-cell-names = "speed_grade";
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
@@ -83,6 +98,7 @@ A53_1: cpu@1 {
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
@@ -101,6 +117,7 @@ A53_2: cpu@2 {
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
@@ -119,6 +136,7 @@ A53_3: cpu@3 {
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {