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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-03 18:12:25 -04:00
arm64: sysreg: Add registers trapped by HDFG{R,W}TR2_EL2
Bulk addition of all the system registers trapped by HDFG{R,W}TR2_EL2.
The descriptions are extracted from the BSD-licenced JSON file part
of the 2025-03 drop from ARM.
Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
@@ -497,12 +497,22 @@
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#define __PMEV_op2(n) ((n) & 0x7)
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#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
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#define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
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#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
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#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
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#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
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#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
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#define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
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#define __SPMEV_op2(n) ((n) & 0x7)
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#define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
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#define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
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#define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
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#define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
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#define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
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#define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
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#define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
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@@ -101,6 +101,17 @@ Res0 63:32
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Field 31:0 DTRTX
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EndSysreg
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Sysreg MDSELR_EL1 2 0 0 4 2
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Res0 63:6
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Field 5:4 BANK
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Res0 3:0
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EndSysreg
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Sysreg MDSTEPOP_EL1 2 0 0 5 2
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Res0 63:32
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Field 31:0 OPCODE
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EndSysreg
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Sysreg OSECCR_EL1 2 0 0 6 2
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Res0 63:32
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Field 31:0 EDECCR
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@@ -111,6 +122,285 @@ Res0 63:1
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Field 0 OSLK
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EndSysreg
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Sysreg SPMACCESSR_EL1 2 0 9 13 3
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UnsignedEnum 63:62 P31
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 61:60 P30
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 59:58 P29
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 57:56 P28
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 55:54 P27
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 53:52 P26
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 51:50 P25
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 49:48 P24
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 47:46 P23
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 45:44 P22
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 43:42 P21
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 41:40 P20
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 39:38 P19
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 37:36 P18
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 35:34 P17
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 33:32 P16
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 31:30 P15
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 29:28 P14
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 27:26 P13
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 25:24 P12
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 23:22 P11
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 21:20 P10
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 19:18 P9
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 17:16 P8
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 15:14 P7
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 13:12 P6
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 11:10 P5
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 9:8 P4
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 7:6 P3
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 5:4 P2
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 3:2 P1
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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UnsignedEnum 1:0 P0
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0b00 TRAP_RW
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0b01 TRAP_W
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0b11 NOTRAP
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EndEnum
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EndSysreg
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Sysreg SPMACCESSR_EL12 2 5 9 13 3
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Mapping SPMACCESSR_EL1
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EndSysreg
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Sysreg SPMIIDR_EL1 2 0 9 13 4
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Res0 63:32
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Field 31:20 ProductID
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Field 19:16 Variant
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Field 15:12 Revision
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Field 11:0 Implementer
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EndSysreg
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Sysreg SPMDEVARCH_EL1 2 0 9 13 5
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Res0 63:32
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Field 31:21 ARCHITECT
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Field 20 PRESENT
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Field 19:16 REVISION
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Field 15:12 ARCHVER
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Field 11:0 ARCHPART
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EndSysreg
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Sysreg SPMDEVAFF_EL1 2 0 9 13 6
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Res0 63:40
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Field 39:32 Aff3
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Field 31 F0V
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Field 30 U
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Res0 29:25
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Field 24 MT
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Field 23:16 Aff2
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Field 15:8 Aff1
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Field 7:0 Aff0
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EndSysreg
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Sysreg SPMCFGR_EL1 2 0 9 13 7
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Res0 63:32
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Field 31:28 NCG
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Res0 27:25
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Field 24 HDBG
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Field 23 TRO
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Field 22 SS
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Field 21 FZO
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Field 20 MSI
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Field 19 RAO
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Res0 18
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Field 17 NA
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Field 16 EX
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Field 15:14 RAZ
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Field 13:8 SIZE
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Field 7:0 N
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EndSysreg
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Sysreg SPMINTENSET_EL1 2 0 9 14 1
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Field 63:0 P
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EndSysreg
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Sysreg SPMINTENCLR_EL1 2 0 9 14 2
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Field 63:0 P
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EndSysreg
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Sysreg PMCCNTSVR_EL1 2 0 14 11 7
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Field 63:0 CCNT
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EndSysreg
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Sysreg PMICNTSVR_EL1 2 0 14 12 0
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Field 63:0 ICNT
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EndSysreg
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Sysreg SPMCR_EL0 2 3 9 12 0
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Res0 63:12
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Field 11 TRO
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Field 10 HDBG
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Field 9 FZO
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Field 8 NA
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Res0 7:5
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Field 4 EX
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Res0 3:2
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Field 1 P
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Field 0 E
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EndSysreg
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Sysreg SPMCNTENSET_EL0 2 3 9 12 1
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Field 63:0 P
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EndSysreg
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Sysreg SPMCNTENCLR_EL0 2 3 9 12 2
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Field 63:0 P
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EndSysreg
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Sysreg SPMOVSCLR_EL0 2 3 9 12 3
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Field 63:0 P
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EndSysreg
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Sysreg SPMZR_EL0 2 3 9 12 4
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Field 63:0 P
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EndSysreg
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Sysreg SPMSELR_EL0 2 3 9 12 5
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Res0 63:10
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Field 9:4 SYSPMUSEL
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Res0 3:2
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Field 1:0 BANK
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EndSysreg
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Sysreg SPMOVSSET_EL0 2 3 9 14 3
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Field 63:0 P
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EndSysreg
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Sysreg SPMSCR_EL1 2 7 9 14 7
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Field 63:32 IMPDEF
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Field 31 RAO
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Res0 30:5
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Field 4 NAO
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Res0 3:1
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Field 0 SO
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EndSysreg
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Sysreg ID_PFR0_EL1 3 0 0 1 0
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Res0 63:32
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UnsignedEnum 31:28 RAS
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@@ -2432,6 +2722,16 @@ Field 1 ExTRE
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Field 0 E0TRE
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EndSysreg
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Sysreg TRCITECR_EL1 3 0 1 2 3
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Res0 63:2
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Field 1 E1E
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Field 0 E0E
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EndSysreg
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Sysreg TRCITECR_EL12 3 5 1 2 3
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Mapping TRCITECR_EL1
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EndSysreg
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Sysreg SMPRI_EL1 3 0 1 2 4
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Res0 63:4
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Field 3:0 PRIORITY
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@@ -2665,6 +2965,16 @@ Field 16 COLL
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Field 15:0 MSS
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EndSysreg
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Sysreg PMSDSFR_EL1 3 0 9 10 4
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Field 63:0 S
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EndSysreg
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Sysreg PMBMAR_EL1 3 0 9 10 5
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Res0 63:10
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Field 9:8 SH
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Field 7:0 Attr
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EndSysreg
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Sysreg PMBIDR_EL1 3 0 9 10 7
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Res0 63:12
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Enum 11:8 EA
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@@ -2678,6 +2988,21 @@ Field 4 P
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Field 3:0 ALIGN
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EndSysreg
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Sysreg TRBMPAM_EL1 3 0 9 11 5
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Res0 63:27
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Field 26 EN
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Field 25:24 MPAM_SP
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Field 23:16 PMG
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Field 15:0 PARTID
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EndSysreg
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Sysreg PMSSCR_EL1 3 0 9 13 3
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Res0 63:33
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Field 32 NC
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Res0 31:1
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Field 0 SS
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EndSysreg
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Sysreg PMUACR_EL1 3 0 9 14 4
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Res0 63:33
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Field 32 F0
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@@ -2685,11 +3010,29 @@ Field 31 C
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Field 30:0 P
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EndSysreg
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Sysreg PMECR_EL1 3 0 9 14 5
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Res0 63:5
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Field 4:3 SSE
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Field 2 KPME
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Field 1:0 PMEE
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EndSysreg
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Sysreg PMIAR_EL1 3 0 9 14 7
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Field 63:0 ADDRESS
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EndSysreg
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Sysreg PMSELR_EL0 3 3 9 12 5
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Res0 63:5
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Field 4:0 SEL
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EndSysreg
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Sysreg PMZR_EL0 3 3 9 13 4
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Res0 63:33
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Field 32 F0
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Field 31 C
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Field 30:0 P
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EndSysreg
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SysregFields CONTEXTIDR_ELx
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Res0 63:32
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Field 31:0 PROCID
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Reference in New Issue
Block a user