mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-12-27 12:21:22 -05:00
Merge branch 'newsoc/axiado' into soc/newsoc
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>: The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53 cores, secure vault, hardware firewall, and AI acceleration engines. This initial support enables basic bring-up of the SoC and evaluation platform with CPU, timer, UART, and I3C functionality. The series begins by adding the "axiado" vendor prefix and compatible strings for the SoC and board. It then introduces the device tree files and minimal ARCH_AXIADO platform support in arm64. * newsoc/axiado: MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation
This commit is contained in:
Arnd Bergmann
23
Documentation/devicetree/bindings/arm/axiado.yaml
Normal file
23
Documentation/devicetree/bindings/arm/axiado.yaml
Normal file
@@ -0,0 +1,23 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/axiado.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Axiado Platforms
|
||||
|
||||
maintainers:
|
||||
- Harshit Shah <hshah@axiado.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: AX3000 based boards
|
||||
items:
|
||||
- enum:
|
||||
- axiado,ax3000-evk # Axiado AX3000 Evaluation Board
|
||||
- const: axiado,ax3000 # Axiado AX3000 SoC
|
||||
|
||||
additionalProperties: true
|
||||
@@ -1,43 +0,0 @@
|
||||
Cadence GPIO controller bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "cdns,gpio-r1p02".
|
||||
- reg: the register base address and size.
|
||||
- #gpio-cells: should be 2.
|
||||
* first cell is the GPIO number.
|
||||
* second cell specifies the GPIO flags, as defined in
|
||||
<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
|
||||
and GPIO_ACTIVE_LOW flags are supported.
|
||||
- gpio-controller: marks the device as a GPIO controller.
|
||||
- clocks: should contain one entry referencing the peripheral clock driving
|
||||
the GPIO controller.
|
||||
|
||||
Optional properties:
|
||||
- ngpios: integer number of gpio lines supported by this controller, up to 32.
|
||||
- interrupts: interrupt specifier for the controllers interrupt.
|
||||
- interrupt-controller: marks the device as an interrupt controller. When
|
||||
defined, interrupts, interrupt-parent and #interrupt-cells
|
||||
are required.
|
||||
- interrupt-cells: should be 2.
|
||||
* first cell is the GPIO number you want to use as an IRQ source.
|
||||
* second cell specifies the IRQ type, as defined in
|
||||
<dt-bindings/interrupt-controller/irq.h>.
|
||||
Currently only level sensitive IRQs are supported.
|
||||
|
||||
|
||||
Example:
|
||||
gpio0: gpio-controller@fd060000 {
|
||||
compatible = "cdns,gpio-r1p02";
|
||||
reg =<0xfd060000 0x1000>;
|
||||
|
||||
clocks = <&gpio_clk>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
84
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
Normal file
84
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
Normal file
@@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence GPIO Controller
|
||||
|
||||
maintainers:
|
||||
- Jan Kotas <jank@cadence.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: cdns,gpio-r1p02
|
||||
- items:
|
||||
- enum:
|
||||
- axiado,ax3000-gpio
|
||||
- const: cdns,gpio-r1p02
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
ngpios:
|
||||
minimum: 1
|
||||
maximum: 32
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
description: |
|
||||
- First cell is the GPIO line number.
|
||||
- Second cell is flags as defined in <dt-bindings/gpio/gpio.h>,
|
||||
only GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW supported.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
description: |
|
||||
- First cell is the GPIO line number used as IRQ.
|
||||
- Second cell is the trigger type, as defined in
|
||||
<dt-bindings/interrupt-controller/irq.h>.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
if:
|
||||
required: [interrupt-controller]
|
||||
then:
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
gpio0: gpio-controller@fd060000 {
|
||||
compatible = "cdns,gpio-r1p02";
|
||||
reg = <0xfd060000 0x1000>;
|
||||
clocks = <&gpio_clk>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
@@ -14,7 +14,12 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cdns,i3c-master
|
||||
oneOf:
|
||||
- const: cdns,i3c-master
|
||||
- items:
|
||||
- enum:
|
||||
- axiado,ax3000-i3c
|
||||
- const: cdns,i3c-master
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -16,9 +16,10 @@ properties:
|
||||
items:
|
||||
- const: xlnx,xuartps
|
||||
- const: cdns,uart-r1p8
|
||||
- description: UART controller for Zynq Ultrascale+ MPSoC
|
||||
items:
|
||||
- const: xlnx,zynqmp-uart
|
||||
- items:
|
||||
- enum:
|
||||
- axiado,ax3000-uart
|
||||
- xlnx,zynqmp-uart
|
||||
- const: cdns,uart-r1p12
|
||||
|
||||
reg:
|
||||
|
||||
@@ -200,6 +200,8 @@ patternProperties:
|
||||
description: Shanghai Awinic Technology Co., Ltd.
|
||||
"^axentia,.*":
|
||||
description: Axentia Technologies AB
|
||||
"^axiado,.*":
|
||||
description: Axiado Corporation
|
||||
"^axis,.*":
|
||||
description: Axis Communications AB
|
||||
"^azoteq,.*":
|
||||
|
||||
@@ -2413,6 +2413,14 @@ F: arch/arm/boot/dts/aspeed/
|
||||
F: arch/arm/mach-aspeed/
|
||||
N: aspeed
|
||||
|
||||
ARM/AXIADO ARCHITECTURE
|
||||
M: Harshit Shah <hshah@axiado.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/axiado.yaml
|
||||
F: arch/arm64/boot/dts/axiado/
|
||||
N: axiado
|
||||
|
||||
ARM/AXM LSI SOC
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
||||
@@ -40,6 +40,12 @@ config ARCH_APPLE
|
||||
This enables support for Apple's in-house ARM SoC family, such
|
||||
as the Apple M1.
|
||||
|
||||
config ARCH_AXIADO
|
||||
bool "Axiado SoC Family"
|
||||
select GPIOLIB
|
||||
help
|
||||
This enables support for Axiado SoC family like AX3000
|
||||
|
||||
menuconfig ARCH_BCM
|
||||
bool "Broadcom SoC Support"
|
||||
|
||||
|
||||
@@ -9,6 +9,7 @@ subdir-y += amlogic
|
||||
subdir-y += apm
|
||||
subdir-y += apple
|
||||
subdir-y += arm
|
||||
subdir-y += axiado
|
||||
subdir-y += bitmain
|
||||
subdir-y += blaize
|
||||
subdir-y += broadcom
|
||||
|
||||
2
arch/arm64/boot/dts/axiado/Makefile
Normal file
2
arch/arm64/boot/dts/axiado/Makefile
Normal file
@@ -0,0 +1,2 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
|
||||
79
arch/arm64/boot/dts/axiado/ax3000-evk.dts
Normal file
79
arch/arm64/boot/dts/axiado/ax3000-evk.dts
Normal file
@@ -0,0 +1,79 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ax3000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Axiado AX3000 EVK";
|
||||
compatible = "axiado,ax3000-evk", "axiado,ax3000";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial3:115200";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
/* Cortex-A53 will use following memory map */
|
||||
reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
|
||||
<0x00000004 0x00000000 0x00000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* GPIO bank 0 - 7 */
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
520
arch/arm64/boot/dts/axiado/ax3000.dtsi
Normal file
520
arch/arm64/boot/dts/axiado/ax3000.dtsi
Normal file
@@ -0,0 +1,520 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
|
||||
/ {
|
||||
model = "Axiado AX3000";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x3c0013a0>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x3c0013a0>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x3c0013a0>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x3c0013a0>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-unified;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_xin: clock-200000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "clk_xin";
|
||||
};
|
||||
|
||||
refclk: clock-125000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
||||
gic500: interrupt-controller@80300000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x00 0x80300000 0x00 0x10000>,
|
||||
<0x00 0x80380000 0x00 0x80000>;
|
||||
ranges;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
/* GPIO Controller banks 0 - 7 */
|
||||
gpio0: gpio-controller@80500000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80500000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@80580000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80580000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio2: gpio-controller@80600000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80600000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio3: gpio-controller@80680000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80680000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio4: gpio-controller@80700000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80700000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio5: gpio-controller@80780000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80780000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio6: gpio-controller@80800000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80800000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio7: gpio-controller@80880000 {
|
||||
compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
|
||||
reg = <0x00 0x80880000 0x00 0x400>;
|
||||
clocks = <&refclk>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I3C Controller 0 - 16 */
|
||||
i3c0: i3c@80500400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80500400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c1: i3c@80500800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80500800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c2: i3c@80580400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80580400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c3: i3c@80580800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80580800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c4: i3c@80600400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80600400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c5: i3c@80600800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80600800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c6: i3c@80680400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80680400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c7: i3c@80680800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80680800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c8: i3c@80700400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80700400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c9: i3c@80700800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80700800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c10: i3c@80780400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80780400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c11: i3c@80780800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80780800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c12: i3c@80800400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80800400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c13: i3c@80800800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80800800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c14: i3c@80880400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80880400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c15: i3c@80880800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80880800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c16: i3c@80620400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80620400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@80520000 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x80520000 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@805a0000 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x805A0000 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@80620000 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x80620000 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@80520800 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x80520800 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_ARCH_ALPINE=y
|
||||
CONFIG_ARCH_APPLE=y
|
||||
CONFIG_ARCH_AXIADO=y
|
||||
CONFIG_ARCH_BCM=y
|
||||
CONFIG_ARCH_BCM2835=y
|
||||
CONFIG_ARCH_BCM_IPROC=y
|
||||
|
||||
Reference in New Issue
Block a user