net: dsa: lantiq_gswip: introduce bitmap for MII ports

Instead of relying on hard-coded numbers for MII ports, introduce
a bitmap for MII ports.
This is done in order to prepare for supporting MaxLinear GSW1xx ICs
which got a different layout of ports.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://patch.msgid.link/019fc8ed06f2317976eac143320d1dc046e8f392.1755878232.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle
2025-08-22 17:11:57 +01:00
committed by Jakub Kicinski
parent 476c001a55
commit dc6156976d
2 changed files with 12 additions and 3 deletions

View File

@@ -183,14 +183,20 @@ static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
int port)
{
/* There's no MII_CFG register for the CPU port */
if (!dsa_is_cpu_port(priv->ds, port))
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
/* MII_CFG register only exists for MII ports */
if (!(priv->hw_info->mii_ports & BIT(port)))
return;
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
}
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
int port)
{
/* MII_PCDU register only exists for MII ports */
if (!(priv->hw_info->mii_ports & BIT(port)))
return;
switch (port) {
case 0:
gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
@@ -1992,12 +1998,14 @@ static void gswip_shutdown(struct platform_device *pdev)
static const struct gswip_hw_info gswip_xrx200 = {
.max_ports = 7,
.allowed_cpu_ports = BIT(6),
.mii_ports = BIT(0) | BIT(1) | BIT(5),
.phylink_get_caps = gswip_xrx200_phylink_get_caps,
};
static const struct gswip_hw_info gswip_xrx300 = {
.max_ports = 7,
.allowed_cpu_ports = BIT(6),
.mii_ports = BIT(0) | BIT(5),
.phylink_get_caps = gswip_xrx300_phylink_get_caps,
};

View File

@@ -216,6 +216,7 @@
struct gswip_hw_info {
int max_ports;
unsigned int allowed_cpu_ports;
unsigned int mii_ports;
void (*phylink_get_caps)(struct dsa_switch *ds, int port,
struct phylink_config *config);
};