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drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL

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Add the missing PHY lane stagger delay programming for ICL-ADL
platforms on TypeC DP outputs.

v2: (Jani)
- Clarify code comment about lane stagger programming.
- Robustify macro calls with parens.

Bspec: 7534, 49533
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-5-imre.deak@intel.com
This commit is contained in:
Imre Deak
2025-02-14 16:19:54 +02:00
parent dcac00e4d6
commit dc2b12b34f
2 changed files with 32 additions and 0 deletions
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29
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@@ -328,9 +328,32 @@ static u32 ddi_buf_phy_link_rate(int port_clock)
}
}
static int dp_phy_lane_stagger_delay(int port_clock)
{
/*
* Return the number of symbol clocks delay used to stagger the
* assertion/desassertion of the port lane enables. The target delay
* time is 100 ns or greater, return the number of symbols specific to
* the provided port_clock (aka link clock) corresponding to this delay
* time, i.e. so that
*
* number_of_symbols * duration_of_one_symbol >= 100 ns
*
* The delay must be applied only on TypeC DP outputs, for everything else
* the delay must be set to 0.
*
* Return the number of link symbols per 100 ns:
* port_clock (10 kHz) -> bits / 100 us
* / symbol_size -> symbols / 100 us
* / 1000 -> symbols / 100 ns
*/
return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);
}
static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -356,6 +379,12 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
if (!intel_tc_port_in_tbt_alt_mode(dig_port))
intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);
intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);
}
}
static int icl_calc_tbt_pll_link(struct intel_display *display,

3
drivers/gpu/drm/i915/i915_reg.h
View File

@@ -3636,6 +3636,9 @@ enum skl_power_gate {
#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
#define DDI_BUF_PORT_REVERSAL (1 << 16)
#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
(symbols))
#define DDI_BUF_IS_IDLE (1 << 7)
#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
#define DDI_A_4_LANES (1 << 4)