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arm64: dts: mediatek: add i2c support for mt8365 SoC

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There are four I2C master channels in MT8365 with a same HW architecture.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20221122-mt8365-i2c-support-v6-1-e1009c8afd53@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Alexandre Mergnat
2023-03-28 11:04:47 +02:00
committed by Matthias Brugger
parent 92d2c23dc2
commit dbf17e13f0
1 changed files with 48 additions and 0 deletions
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48
arch/arm64/boot/dts/mediatek/mt8365.dtsi
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@@ -282,6 +282,42 @@ pwm: pwm@11006000 {
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi: spi@1100a000 {
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
reg = <0 0x1100a000 0 0x100>;
@@ -295,6 +331,18 @@ spi: spi@1100a000 {
status = "disabled";
};
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssusb: usb@11201000 {
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;