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arm64: dts: hip05: Add L2 cache topology

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The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Kefeng Wang
2016-01-29 16:39:01 +08:00
committed by Wei Xu
parent 92e963f50f
commit dbb58d0f79
1 changed files with 32 additions and 0 deletions
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32
arch/arm64/boot/dts/hisilicon/hip05.dtsi
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@@ -90,6 +90,7 @@ cpu0: cpu@20000 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20000>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu1: cpu@20001 {
@@ -97,6 +98,7 @@ cpu1: cpu@20001 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20001>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu2: cpu@20002 {
@@ -104,6 +106,7 @@ cpu2: cpu@20002 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20002>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu3: cpu@20003 {
@@ -111,6 +114,7 @@ cpu3: cpu@20003 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20003>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu4: cpu@20100 {
@@ -118,6 +122,7 @@ cpu4: cpu@20100 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20100>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu5: cpu@20101 {
@@ -125,6 +130,7 @@ cpu5: cpu@20101 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20101>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu6: cpu@20102 {
@@ -132,6 +138,7 @@ cpu6: cpu@20102 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20102>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu7: cpu@20103 {
@@ -139,6 +146,7 @@ cpu7: cpu@20103 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20103>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu8: cpu@20200 {
@@ -146,6 +154,7 @@ cpu8: cpu@20200 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20200>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu9: cpu@20201 {
@@ -153,6 +162,7 @@ cpu9: cpu@20201 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20201>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu10: cpu@20202 {
@@ -160,6 +170,7 @@ cpu10: cpu@20202 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20202>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu11: cpu@20203 {
@@ -167,6 +178,7 @@ cpu11: cpu@20203 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20203>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
};
cpu12: cpu@20300 {
@@ -174,6 +186,7 @@ cpu12: cpu@20300 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20300>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cpu13: cpu@20301 {
@@ -181,6 +194,7 @@ cpu13: cpu@20301 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20301>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cpu14: cpu@20302 {
@@ -188,6 +202,7 @@ cpu14: cpu@20302 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20302>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cpu15: cpu@20303 {
@@ -195,6 +210,23 @@ cpu15: cpu@20303 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x20303>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
};