mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-16 10:11:38 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amd/ras: Add table reset func for pmfw eeprom

Browse Source 
add table reset func for pmfw eeprom, add smu eeprom control
structure

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gangliang Xie
2025-12-15 12:34:41 +08:00
committed by Alex Deucher
parent 0e5eaa8d8d
commit db217d08af
4 changed files with 63 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/ras/rascore/ras.h
View File

@@ -313,6 +313,7 @@ struct ras_core_context {
bool ras_eeprom_supported;
struct ras_eeprom_control ras_eeprom;
struct ras_fw_eeprom_control ras_fw_eeprom;
struct ras_psp ras_psp;
struct ras_umc ras_umc;

9
drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
View File

@@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core,
if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
if (ras_eeprom_reset_table(ras_core))
return RAS_CMD__ERROR_GENERIC;
if (ras_fw_eeprom_supported(ras_core)) {
if (ras_fw_eeprom_reset_table(ras_core))
return RAS_CMD__ERROR_GENERIC;
} else {
if (ras_eeprom_reset_table(ras_core))
return RAS_CMD__ERROR_GENERIC;
}
if (ras_umc_clean_badpage_data(ras_core))
return RAS_CMD__ERROR_GENERIC;

29
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
View File

@@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
return sys_func->mp1_send_eeprom_msg(ras_core,
RAS_SMU_EraseRasTable, 0, result);
}
int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
{
struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
u32 erase_res = 0;
int res;
mutex_lock(&control->ras_tbl_mutex);
res = ras_fw_erase_ras_table(ras_core, &erase_res);
if (res || erase_res) {
RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",
res, erase_res);
if (!res)
res = -EIO;
}
control->ras_num_recs = 0;
control->bad_channel_bitmap = 0;
ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
&control->ras_num_recs);
ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
&control->bad_channel_bitmap);
control->update_channel_flag = false;
mutex_unlock(&control->ras_tbl_mutex);
return res;
}

26
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
View File

@@ -24,6 +24,31 @@
#ifndef __RAS_EEPROM_FW_H__
#define __RAS_EEPROM_FW_H__
struct ras_fw_eeprom_control {
uint32_t version;
/* record threshold */
int record_threshold_config;
uint32_t record_threshold_count;
bool update_channel_flag;
/* Number of records in the table.
*/
u32 ras_num_recs;
/* Maximum possible number of records
* we could store, i.e. the maximum capacity
* of the table.
*/
u32 ras_max_record_count;
/* Protect table access via this mutex.
*/
struct mutex ras_tbl_mutex;
/* Record channel info which occurred bad pages
*/
u32 bad_channel_bitmap;
};
void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
@@ -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
uint16_t index, uint64_t *ipid);
int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
uint32_t *result);
int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
#endif