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net: dsa: microchip: Use regs[] to access REG_PTP_SUBNANOSEC_RATE

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Accesses to the PTP_SUBNANOSEC_RATE register are done through a
hardcoded address which doesn't match with the KSZ8463's register
layout.

Add a new entry for the PTP_SUBNANOSEC_RATE register in the regs[]
tables.
Use the regs[] table to retrieve the PTP_SUBNANOSEC_RATE register
address when accessing it.
Remove the macro defining the address to prevent further use.

Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Link: https://patch.msgid.link/20260105-ksz-rework-v1-7-a68df7f57375@bootlin.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Bastien Curutchet (Schneider Electric)
2026-01-05 14:08:06 +01:00
committed by Paolo Abeni
parent 5b1fe74fac
commit d99c1a01ac
4 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/dsa/microchip/ksz_common.c
View File

@@ -573,6 +573,7 @@ static const u16 ksz8463_regs[] = {
[PTP_RTC_NANOSEC] = 0x0604,
[PTP_RTC_SEC] = 0x0608,
[PTP_RTC_SUB_NANOSEC] = 0x060C,
[PTP_SUBNANOSEC_RATE] = 0x0610,
};
static const u32 ksz8463_masks[] = {
@@ -811,6 +812,7 @@ static const u16 ksz9477_regs[] = {
[PTP_RTC_SUB_NANOSEC] = 0x0502,
[PTP_RTC_NANOSEC] = 0x0504,
[PTP_RTC_SEC] = 0x0508,
[PTP_SUBNANOSEC_RATE] = 0x050C,
};
static const u32 ksz9477_masks[] = {

1
drivers/net/dsa/microchip/ksz_common.h
View File

@@ -275,6 +275,7 @@ enum ksz_regs {
PTP_RTC_NANOSEC,
PTP_RTC_SEC,
PTP_RTC_SUB_NANOSEC,
PTP_SUBNANOSEC_RATE,
};
enum ksz_masks {

2
drivers/net/dsa/microchip/ksz_ptp.c
View File

@@ -742,7 +742,7 @@ static int ksz_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
if (!negative)
data32 |= PTP_RATE_DIR;
ret = ksz_write32(dev, REG_PTP_SUBNANOSEC_RATE, data32);
ret = ksz_write32(dev, regs[PTP_SUBNANOSEC_RATE], data32);
if (ret)
goto unlock;

3
drivers/net/dsa/microchip/ksz_ptp_reg.h
View File

@@ -28,8 +28,7 @@
#define PTP_RTC_SUB_NANOSEC_M 0x0007
#define PTP_RTC_0NS 0x00
#define REG_PTP_SUBNANOSEC_RATE 0x050C
/* REG_PTP_SUBNANOSEC_RATE */
#define PTP_SUBNANOSEC_M 0x3FFFFFFF
#define PTP_RATE_DIR BIT(31)
#define PTP_TMP_RATE_ENABLE BIT(30)