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drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twice

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For vega20, there are two UVD rings which share one powerplay instance.
Under some case(two rings used parallel), the uvd dpm is disabled twice
which causes the SMC hang.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
2018-07-19 18:40:25 +08:00
committed by Alex Deucher
parent be6a55a11a
commit d940def9ab
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
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@@ -2464,6 +2464,9 @@ static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
if (data->vce_power_gated == bgate)
return ;
data->vce_power_gated = bgate;
vega20_enable_disable_vce_dpm(hwmgr, !bgate);
}
@@ -2472,6 +2475,9 @@ static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
if (data->uvd_power_gated == bgate)
return ;
data->uvd_power_gated = bgate;
vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
}